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dc.contributor.authorGómez Fernández, Sergio
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2013-10-16T16:15:17Z
dc.date.created2013-08-15
dc.date.issued2013-08-15
dc.identifier.citationGomez, S.; Moll, F. Yield estimation model for lithography hotspot distortions. "Electronics Letters", 15 Agost 2013, vol. 49, núm. 17, p. 1066-1068.
dc.identifier.issn0013-5194
dc.identifier.urihttp://hdl.handle.net/2117/20390
dc.description.abstractA yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield loss. The application of the yield model is demonstrated for three different layout configurations showing that unidimensional designs may improve manufacturing yield.
dc.format.extent3 p.
dc.language.isoeng
dc.publisherInstitution of Electrical Engineers
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subjectÀrees temàtiques de la UPC::Enginyeria dels materials
dc.subject.otherHot spot
dc.subject.otherManufacturing yield
dc.subject.otherYield estimation
dc.subject.otherYield loss
dc.subject.otherYield modeling
dc.titleYield estimation model for lithography hotspot distortions
dc.typeArticle
dc.subject.lemacLitografia per feix d'electrons
dc.subject.lemacLitografia
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1049/el.2013.0469
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6583109
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac12763134
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248538/EU/SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms/SYNAPTIC
dc.date.lift10000-01-01
local.citation.authorGomez, S.; Moll, F.
local.citation.publicationNameElectronics Letters
local.citation.volume49
local.citation.number17
local.citation.startingPage1066
local.citation.endingPage1068


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