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Yield estimation model for lithography hotspot distortions
dc.contributor.author | Gómez Fernández, Sergio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2013-10-16T16:15:17Z |
dc.date.created | 2013-08-15 |
dc.date.issued | 2013-08-15 |
dc.identifier.citation | Gomez, S.; Moll, F. Yield estimation model for lithography hotspot distortions. "Electronics Letters", 15 Agost 2013, vol. 49, núm. 17, p. 1066-1068. |
dc.identifier.issn | 0013-5194 |
dc.identifier.uri | http://hdl.handle.net/2117/20390 |
dc.description.abstract | A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield loss. The application of the yield model is demonstrated for three different layout configurations showing that unidimensional designs may improve manufacturing yield. |
dc.format.extent | 3 p. |
dc.language.iso | eng |
dc.publisher | Institution of Electrical Engineers |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Àrees temàtiques de la UPC::Enginyeria dels materials |
dc.subject.other | Hot spot |
dc.subject.other | Manufacturing yield |
dc.subject.other | Yield estimation |
dc.subject.other | Yield loss |
dc.subject.other | Yield modeling |
dc.title | Yield estimation model for lithography hotspot distortions |
dc.type | Article |
dc.subject.lemac | Litografia per feix d'electrons |
dc.subject.lemac | Litografia |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1049/el.2013.0469 |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6583109 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 12763134 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/248538/EU/SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms/SYNAPTIC |
dc.date.lift | 10000-01-01 |
local.citation.author | Gomez, S.; Moll, F. |
local.citation.publicationName | Electronics Letters |
local.citation.volume | 49 |
local.citation.number | 17 |
local.citation.startingPage | 1066 |
local.citation.endingPage | 1068 |
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