Yield estimation model for lithography hotspot distortions
PublisherInstitution of Electrical Engineers
Rights accessRestricted access - publisher's policy
European Commisision's projectSYNAPTIC - SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms (EC-FP7-248538)
A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield loss. The application of the yield model is demonstrated for three different layout configurations showing that unidimensional designs may improve manufacturing yield.
CitationGomez, S.; Moll, F. Yield estimation model for lithography hotspot distortions. "Electronics Letters", 15 Agost 2013, vol. 49, núm. 17, p. 1066-1068.
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