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Physical planning for the architectural exploration of large-scale chip multiprocessors
dc.contributor.author | San Pedro Martín, Javier de |
dc.contributor.author | Nikitin, Nikita |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Petit Silvestre, Jordi |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics |
dc.date.accessioned | 2013-10-04T10:16:34Z |
dc.date.created | 2013 |
dc.date.issued | 2013 |
dc.identifier.citation | De San Pedro, J. [et al.]. Physical planning for the architectural exploration of large-scale chip multiprocessors. A: IEEE/ACM International Symposium on Networks-on-Chip. "2013 Seventh IEEE/ACM International Symposium on Networks on Chip (NoCS)". Tempe: 2013, p. 1-2. |
dc.identifier.isbn | 978-1-4673-6491-1 |
dc.identifier.uri | http://hdl.handle.net/2117/20300 |
dc.description.abstract | This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout constraints that enforce regularity in the interconnect networks. Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity. The experiments demonstrate the impact of physical parameters in the selection of the most efficient architectures. Thus, the integrated flow contributes to deliver physically-viable architectures and simplify the complex design closure of large-scale CMPs. |
dc.format.extent | 2 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
dc.subject.lcsh | Circuit layout |
dc.subject.lcsh | Network routing |
dc.subject.other | Microprocessor chips Computer networks Information systems |
dc.title | Physical planning for the architectural exploration of large-scale chip multiprocessors |
dc.type | Conference lecture |
dc.subject.lemac | CMP |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/NoCS.2013.6558399 |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 12790941 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | De San Pedro, J.; Nikitin, N.; Cortadella, J.; Petit, J. |
local.citation.contributor | IEEE/ACM International Symposium on Networks-on-Chip |
local.citation.pubplace | Tempe |
local.citation.publicationName | 2013 Seventh IEEE/ACM International Symposium on Networks on Chip (NoCS) |
local.citation.startingPage | 1 |
local.citation.endingPage | 2 |