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dc.contributor.authorCaballero, Diego
dc.contributor.authorDuran González, Alejandro
dc.contributor.authorMartorell Bofill, Xavier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2013-10-03T18:49:02Z
dc.date.created2013
dc.date.issued2013
dc.identifier.citationCaballero, D.; Duran, A.; Martorell, X. An OpenMP* barrier using SIMD instructions for Intel® Xeon Phi™ coprocessor. A: International Workshop on OpenMP. "OpenMP in the era of low power devices and accelerators: 9th International Workshop on OpenMP, IWOMP 2013: Canberra, ACT, Australia: September 2013: Proceedings". Canberra: Springer, 2013, p. 99-113.
dc.identifier.isbn978-3-642-40697-3
dc.identifier.urihttp://hdl.handle.net/2117/20295
dc.description.abstractBarrier synchronisation is a widely-studied topic since the supercomputer era due to its significant impact on the overall performance of parallel applications. With the current shift to many-core architectures, such as the Intel® Many Integrated Core Architecture, software barriers need to be revisited from an on-chip point of view to exploit their new specific resources. In this paper, we propose a tree-based barrier that takes advantage of SIMD instructions and the inter-thread cache locality provided by the 4-way SMT of the Intel® Xeon PhiTM coprocessor. Our SIMD approach shows a speed-up of up to 2.84x over the default Intel OpenMP* barrier in the EPCC barrier microbenchmark. It also improves by up to 60% and 21% the Livermore Loop kernel number six and the NAS MG benchmark, respectively.
dc.format.extent15 p.
dc.language.isoeng
dc.publisherSpringer
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshSupercomputers
dc.subject.otherBarrier
dc.subject.othercombining tree
dc.subject.otherIntel® Many Integrated Core Architecture
dc.subject.otherIntel® Xeon Phi™ coprocessor
dc.subject.othermany-cores
dc.subject.otherOpenMP*
dc.subject.otherSIMD
dc.subject.othersynchronisation primitives
dc.titleAn OpenMP* barrier using SIMD instructions for Intel® Xeon Phi™ coprocessor
dc.typeConference report
dc.subject.lemacSupercomputadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1007/978-3-642-40698-0_8
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://link.springer.com/chapter/10.1007%2F978-3-642-40698-0_8
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac12792350
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
dc.date.lift10000-01-01
local.citation.authorCaballero, D.; Duran, A.; Martorell, X.
local.citation.contributorInternational Workshop on OpenMP
local.citation.pubplaceCanberra
local.citation.publicationNameOpenMP in the era of low power devices and accelerators: 9th International Workshop on OpenMP, IWOMP 2013: Canberra, ACT, Australia: September 2013: Proceedings
local.citation.startingPage99
local.citation.endingPage113


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