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An OpenMP* barrier using SIMD instructions for Intel® Xeon Phi™ coprocessor
dc.contributor.author | Caballero, Diego |
dc.contributor.author | Duran González, Alejandro |
dc.contributor.author | Martorell Bofill, Xavier |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2013-10-03T18:49:02Z |
dc.date.created | 2013 |
dc.date.issued | 2013 |
dc.identifier.citation | Caballero, D.; Duran, A.; Martorell, X. An OpenMP* barrier using SIMD instructions for Intel® Xeon Phi™ coprocessor. A: International Workshop on OpenMP. "OpenMP in the era of low power devices and accelerators: 9th International Workshop on OpenMP, IWOMP 2013: Canberra, ACT, Australia: September 2013: Proceedings". Canberra: Springer, 2013, p. 99-113. |
dc.identifier.isbn | 978-3-642-40697-3 |
dc.identifier.uri | http://hdl.handle.net/2117/20295 |
dc.description.abstract | Barrier synchronisation is a widely-studied topic since the supercomputer era due to its significant impact on the overall performance of parallel applications. With the current shift to many-core architectures, such as the Intel® Many Integrated Core Architecture, software barriers need to be revisited from an on-chip point of view to exploit their new specific resources. In this paper, we propose a tree-based barrier that takes advantage of SIMD instructions and the inter-thread cache locality provided by the 4-way SMT of the Intel® Xeon PhiTM coprocessor. Our SIMD approach shows a speed-up of up to 2.84x over the default Intel OpenMP* barrier in the EPCC barrier microbenchmark. It also improves by up to 60% and 21% the Livermore Loop kernel number six and the NAS MG benchmark, respectively. |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.publisher | Springer |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject.lcsh | Supercomputers |
dc.subject.other | Barrier |
dc.subject.other | combining tree |
dc.subject.other | Intel® Many Integrated Core Architecture |
dc.subject.other | Intel® Xeon Phi™ coprocessor |
dc.subject.other | many-cores |
dc.subject.other | OpenMP* |
dc.subject.other | SIMD |
dc.subject.other | synchronisation primitives |
dc.title | An OpenMP* barrier using SIMD instructions for Intel® Xeon Phi™ coprocessor |
dc.type | Conference report |
dc.subject.lemac | Supercomputadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1007/978-3-642-40698-0_8 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://link.springer.com/chapter/10.1007%2F978-3-642-40698-0_8 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 12792350 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.date.lift | 10000-01-01 |
local.citation.author | Caballero, D.; Duran, A.; Martorell, X. |
local.citation.contributor | International Workshop on OpenMP |
local.citation.pubplace | Canberra |
local.citation.publicationName | OpenMP in the era of low power devices and accelerators: 9th International Workshop on OpenMP, IWOMP 2013: Canberra, ACT, Australia: September 2013: Proceedings |
local.citation.startingPage | 99 |
local.citation.endingPage | 113 |