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Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm
dc.contributor.author | Amat Bertran, Esteve |
dc.contributor.author | García Almudéver, Carmen |
dc.contributor.author | Aymerich Capdevila, Nivard |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2013-09-19T12:30:29Z |
dc.date.available | 2013-09-19T12:30:29Z |
dc.date.created | 2012 |
dc.date.issued | 2012 |
dc.identifier.citation | Amat, E. [et al.]. Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm. A: Conference on Design of Circuits and Integrated Systems. "Proceedings of DCIS 2012 : XXVII Design of Circuits and Integrated Systems Conference". Avignon: 2012, p. 1-5. |
dc.identifier.uri | http://hdl.handle.net/2117/20163 |
dc.description | Best DCIS Paper Award 2012 |
dc.description.abstract | 3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability. |
dc.format.extent | 5 p. |
dc.language.iso | eng |
dc.subject.lcsh | Dynamic random-access memory |
dc.subject.lcsh | DRAM |
dc.subject.other | variability |
dc.subject.other | DRAM |
dc.subject.other | temperature |
dc.title | Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm |
dc.type | Conference report |
dc.subject.lemac | Memòries electròniques d'accés aleatori |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.description.peerreviewed | Peer Reviewed |
dc.description.awardwinning | Award-winning |
dc.rights.access | Open Access |
local.identifier.drac | 12764214 |
dc.description.version | Preprint |
local.citation.author | Amat, E.; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, J.A. |
local.citation.contributor | Conference on Design of Circuits and Integrated Systems |
local.citation.pubplace | Avignon |
local.citation.publicationName | Proceedings of DCIS 2012 : XXVII Design of Circuits and Integrated Systems Conference |
local.citation.startingPage | 1 |
local.citation.endingPage | 5 |