Impact of gate tunnelling leakage on CMOS circuits with full open defects
PublisherInstitution of Electrical Engineers
Rights accessOpen Access
Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.
Electronics Letter of the Month
CitationRodriguez, R. [et al.]. Impact of gate tunnelling leakage on CMOS circuits with full open defects. "Electronics Letters", Octubre 2007, vol. 43, núm. Issue 21, p. 1140-1141.
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder