Synthesis of IDDQ-Testable Circuits: Integrating Built-in Current Sensors
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hdl:2117/20064
Tipus de documentText en actes de congrés
Data publicació1995
Condicions d'accésAccés obert
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Reconeixement-NoComercial-SenseObraDerivada 3.0 Espanya
Abstract
"On-Chip" I_{DDQ} testing by the incorporation of Built-In Current (BIC) sensors has some advantages over "off-chip" techniques. However, the integration of sensors poses analog design problems which are hard to be solved by a digital designer. The automatic incorporation of the sensors using parameterized BIC cells could be a promising alternative. The work reported here identifies partitioning criteria to guide the synthesis of I_{DDQ}-testable circuits. The circuit must be partitioned, such that the defective I_{DDQ} is observable, and the power
supply voltage perturbation is within specified limits. In addition to these constraints, also cost criteria are considered: circuit extra delay, area overhead of the BIC sensors, connectivity costs of the test circuitry, and the test application time. The parameters are estimated based on logical as well as electrical level information of the target cell library to be used in the technology mapping phase of the synthesis process. The resulting cost function is optimized by an evolution-based algorithm. When run over large benchmark circuits our method gives significantly superior results to those obtained using simpler and less comprehensive partitioning methods.
CitacióWunderlich, H. [et al.]. Synthesis of IDDQ-testable circuits: integrating built-in current sensors. A: IEEE European Design and Automation Conf.. "Proc. IEEE European Design and Automation Conf.". 1995, p. 573-580.
Col·leccions
- QINE - Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades - Ponències/Comunicacions de congressos [60]
- QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat - Ponències/Comunicacions de congressos [78]
- Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos [1.713]
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