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Producer-consumer: the programming model for future many-core processors
dc.contributor.author | Prat Pérez, Arnau |
dc.contributor.author | Domínguez Sal, David |
dc.contributor.author | Larriba Pey, Josep |
dc.contributor.author | Troncoso, Pedro |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2013-07-30T12:17:36Z |
dc.date.created | 2013 |
dc.date.issued | 2013 |
dc.identifier.citation | Prat, A. [et al.]. Producer-consumer: the programming model for future many-core processors. A: International Conference on Architecture of Computing Systems. "ARCS 2013: 26th International Conference on Architecture of Computing Systems: Prague, Czech Republic: February 19-22, 2013: proceedings". Praga: Springer, 2013, p. 110-121. |
dc.identifier.isbn | 978-364236423-5 |
dc.identifier.uri | http://hdl.handle.net/2117/20034 |
dc.description.abstract | The massive addition of cores on a chip is adding more pressure to the accesses to main memory. In order to avoid this bottleneck, we propose the use of a simple producer-consumer model, which allows for the temporary results to be transferred directly from one task to another. These data transfer operations are performed within the chip, using on-chip memory, thus avoiding costly off-chip memory accesses. We implement this model on a real many-core processor, the 48-core Intel Single-chip Cloud Computer processor using its on-chip memory facilities. We find that the Producer-Consumer model adapts to such architectures and allow to achieve good task and data parallelism. For the evaluation of the proposed platform we implement a graph-based application using the Producer- Consumer model. Our tests show that the model scales very well as it takes advantage of the on-chip memory. The execution times of our implementation are up to 9 times faster than the baseline implementation, which relies on storing the temporary results to main memory. |
dc.format.extent | 12 p. |
dc.language.iso | eng |
dc.publisher | Springer |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Computer architecture |
dc.subject.other | Data parallelism |
dc.subject.other | Execution time |
dc.subject.other | Graph-based |
dc.subject.other | Main memory |
dc.subject.other | Many-core processors |
dc.subject.other | Model scale |
dc.subject.other | Off-chip memories |
dc.subject.other | On chip memory |
dc.subject.other | Programming models |
dc.subject.other | Single-chip cloud computers |
dc.title | Producer-consumer: the programming model for future many-core processors |
dc.type | Conference report |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.contributor.group | Universitat Politècnica de Catalunya. DAMA-UPC - Data Management Group |
dc.identifier.doi | 10.1007/978-3-642-36424-2_10 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://dl.acm.org/citation.cfm?id=2450037 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 11858005 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.date.lift | 10000-01-01 |
local.citation.author | Prat, A.; Dominguez, D.; Larriba, J.; Troncoso, P. |
local.citation.contributor | International Conference on Architecture of Computing Systems |
local.citation.pubplace | Praga |
local.citation.publicationName | ARCS 2013: 26th International Conference on Architecture of Computing Systems: Prague, Czech Republic: February 19-22, 2013: proceedings |
local.citation.startingPage | 110 |
local.citation.endingPage | 121 |