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Framework for a productive performance optimization
dc.contributor.author | Servat, Harald |
dc.contributor.author | Llort, German |
dc.contributor.author | Huck, Kevin A. |
dc.contributor.author | Giménez Lucas, Judit |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2013-07-26T15:41:56Z |
dc.date.created | 2013-08 |
dc.date.issued | 2013-08 |
dc.identifier.citation | Servat, H. [et al.]. Framework for a productive performance optimization. "Parallel computing", Agost 2013, vol. 39, núm. 8, p. 336-353. |
dc.identifier.issn | 0167-8191 |
dc.identifier.uri | http://hdl.handle.net/2117/20012 |
dc.description.abstract | Modern supercomputers deliver large computational power, but it is difficult for an application to exploit such power. One factor that limits the application performance is the single node performance. While many performance tools use the microprocessor performance counters to provide insights on serial node performance issues, the complex semantics of these counters pose an obstacle to an inexperienced developer. We present a framework that allows easy identification and qualification of serial node performance bottlenecks in parallel applications. The output of the framework is precise and it is capable of correlating performance inefficiencies with small regions of code within the application. The framework not only points to regions of code but also simplifies the semantics of the performance counters into metrics that refer to processor functional units. With such information the developer can focus on the identified code and improve it by knowing which processor execution unit is degrading the performance. To demonstrate the usefulness of the framework we apply it to three already optimized applications using realistic inputs and, according to the results, modify their source code. By doing modifications that require little effort, we successfully increase the applications’ performance from 10% to 30% and thus shorten the time required to reach the solution and/or allow facing increased problem sizes. |
dc.format.extent | 18 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Programació |
dc.subject.lcsh | Supercomputers |
dc.subject.lcsh | Parallel programming (Computer science) |
dc.subject.other | Application tuning |
dc.subject.other | Instrumentation |
dc.subject.other | Performance analysis |
dc.subject.other | Performance models |
dc.subject.other | Performance tools |
dc.subject.other | Sampling |
dc.title | Framework for a productive performance optimization |
dc.type | Article |
dc.subject.lemac | Supercomputadors |
dc.subject.lemac | Programació en paral·lel (Informàtica) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1016/j.parco.2013.05.004 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://www.sciencedirect.com/science/article/pii/S0167819113000707 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 12674931 |
dc.description.version | Preprint |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/283493/EU/PRACE/PRACE-2IP |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.date.lift | 10000-01-01 |
local.citation.author | Servat, H.; Llort, G.; Huck, K.; Gimenez, J.; Labarta, J. |
local.citation.publicationName | Parallel computing |
local.citation.volume | 39 |
local.citation.number | 8 |
local.citation.startingPage | 336 |
local.citation.endingPage | 353 |
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