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Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations
dc.contributor.author | Jaksic, Zoran |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2013-07-11T14:49:26Z |
dc.date.created | 2012-12 |
dc.date.issued | 2012-12 |
dc.identifier.citation | Jaksic, Z.; Canal, R. Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations. "IEEE transactions on electron devices", Desembre 2012, vol. 60, núm. 1, p. 49-55. |
dc.identifier.issn | 0018-9383 |
dc.identifier.uri | http://hdl.handle.net/2117/19931 |
dc.description.abstract | We explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. We propose a method to incorporate them into a BSIM-CMG model card for time-efficient simulation. We analyze cells with different fin numbers, supply voltages, and temperatures. Results show a 1.8× improvement of RSNM for 8T SRAM cells, the need for stronger pull-downs to secure read stability in 6Ts, and high leakage sensitivity to temperature (10× between 40°C and 100°C). As a specific example, we show how the RSNM of a 6T SRAM cell can be improved by using back-gate biasing techniques for independent-gate FinFETs. We show how WLMN is increased by reducing the strength of pull-up transistors when reverse back-gate biasing is applied on it and how the RSNM can be increased by reducing the strength of access transistor by reverse back-gate biasing of pass-gate transistors. When combining these two techniques, RSNM can be improved up to 25% without compromising cell write ability for any sample. In general, when compared to previous technologies, read stability is untouched, writeability is reduced, and leakage keeps stable. |
dc.format.extent | 7 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Hardware |
dc.subject.lcsh | Semiconductor storage devices |
dc.subject.other | 6T cell |
dc.subject.other | 8T cell |
dc.subject.other | FinFET |
dc.subject.other | leakage |
dc.subject.other | process variation |
dc.subject.other | SRAM |
dc.title | Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations |
dc.type | Article |
dc.subject.lemac | Ordinadors -- Memòries semiconductores |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/TED.2012.2226095 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06374661 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 11251277 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS |
dc.date.lift | 10000-01-01 |
local.citation.author | Jaksic, Z.; Canal, R. |
local.citation.publicationName | IEEE transactions on electron devices |
local.citation.volume | 60 |
local.citation.number | 1 |
local.citation.startingPage | 49 |
local.citation.endingPage | 55 |
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