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dc.contributor.authorJaksic, Zoran
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2013-07-11T14:49:26Z
dc.date.created2012-12
dc.date.issued2012-12
dc.identifier.citationJaksic, Z.; Canal, R. Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations. "IEEE transactions on electron devices", Desembre 2012, vol. 60, núm. 1, p. 49-55.
dc.identifier.issn0018-9383
dc.identifier.urihttp://hdl.handle.net/2117/19931
dc.description.abstractWe explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. We propose a method to incorporate them into a BSIM-CMG model card for time-efficient simulation. We analyze cells with different fin numbers, supply voltages, and temperatures. Results show a 1.8× improvement of RSNM for 8T SRAM cells, the need for stronger pull-downs to secure read stability in 6Ts, and high leakage sensitivity to temperature (10× between 40°C and 100°C). As a specific example, we show how the RSNM of a 6T SRAM cell can be improved by using back-gate biasing techniques for independent-gate FinFETs. We show how WLMN is increased by reducing the strength of pull-up transistors when reverse back-gate biasing is applied on it and how the RSNM can be increased by reducing the strength of access transistor by reverse back-gate biasing of pass-gate transistors. When combining these two techniques, RSNM can be improved up to 25% without compromising cell write ability for any sample. In general, when compared to previous technologies, read stability is untouched, writeability is reduced, and leakage keeps stable.
dc.format.extent7 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshSemiconductor storage devices
dc.subject.other6T cell
dc.subject.other8T cell
dc.subject.otherFinFET
dc.subject.otherleakage
dc.subject.otherprocess variation
dc.subject.otherSRAM
dc.titleComparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations
dc.typeArticle
dc.subject.lemacOrdinadors -- Memòries semiconductores
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/TED.2012.2226095
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06374661
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac11251277
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS
dc.date.lift10000-01-01
local.citation.authorJaksic, Z.; Canal, R.
local.citation.publicationNameIEEE transactions on electron devices
local.citation.volume60
local.citation.number1
local.citation.startingPage49
local.citation.endingPage55


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Attribution-NonCommercial-NoDerivs 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain