Vector extensions for decision support DBMS acceleration
dc.contributor.author | Hayes, Timothy |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2013-05-16T09:15:37Z |
dc.date.created | 2012 |
dc.date.issued | 2012 |
dc.identifier.citation | Hayes, T. [et al.]. Vector extensions for decision support DBMS acceleration. A: IEEE/ACM International Symposium on Microarchitecture. "Proceedings of the 45th Annual International Symposium on Microarchitecture". Vancouver: IEEE, 2012, p. 166-176. |
dc.identifier.uri | http://hdl.handle.net/2117/19276 |
dc.description.abstract | Database management systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centres. As a result of this criticality, efficient execution of DBMS engines has become an important area of investigation. This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64 microprocessors using vector ISA exten- sions. In the first step, a leading DSS DBMS is analysed for potential data-level parallelism. We discuss why the existing multimedia SIMD extensions (SSE/AVX) are not suitable for capturing this parallelism and propose a complementary instruction set reminiscent of classical vector architectures. The instruction set is implemented using unin- trusive modifications to a modern x86-64 microarchitecture tailored for DSS DBMS. The ISA and microarchitecture are evaluated using a cycle-accurate x86-64 microarchitectural simulator coupled with a highly-detailed memory simulator. We have found a single oper- ator is responsible for 41% of total execution time for the TPC-H DSS benchmark. Our results show performance speedups between 1.94x and 4.56x for an implementation of this operator run with our proposed hardware modifications. |
dc.format.extent | 11 p. |
dc.language.iso | eng |
dc.publisher | IEEE |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Computer architecture |
dc.title | Vector extensions for decision support DBMS acceleration |
dc.type | Conference report |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/MICRO.2012.24 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://delivery.acm.org/10.1145/2460000/2457495/4924a166.pdf?ip=147.83.95.30&acc=ACTIVE%20SERVICE&key=C2716FEBFA981EF161F5D4B6734BF3A99E438D22375C4622&CFID=330243680&CFTOKEN=42804320&__acm__=1368695302_6c5e6c080bb6e9edd9c41abdd561d656 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 11131476 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Hayes, T.; Palomar, O.; Unsal, O.; Cristal-Kestelman, A.; Valero, M. |
local.citation.contributor | IEEE/ACM International Symposium on Microarchitecture |
local.citation.pubplace | Vancouver |
local.citation.publicationName | Proceedings of the 45th Annual International Symposium on Microarchitecture |
local.citation.startingPage | 166 |
local.citation.endingPage | 176 |
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