Mostra el registre d'ítem simple
Design of an AXI-SDRAM interface IP in a RISC-V processor
dc.contributor | Moll Echeto, Francisco de Borja |
dc.contributor.author | Marimon Illana, Joan |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2020-07-02T09:44:21Z |
dc.date.available | 2020-07-02T09:44:21Z |
dc.date.issued | 2020-05 |
dc.identifier.uri | http://hdl.handle.net/2117/192250 |
dc.description.abstract | PreDRAC is a RISC-V based SoC developed with the collaboration of the BSC, CIC-IPN, IMB-CNM (CSIC) and UPC. On its first version, sent to fabricate on May 2019, it used a custom interface to access main memory through an FPGA. Access to memory is critical to the performance of a processor and a AXI-SDRAM interface IP to be integrated into a future revision of the chip has been designed. No specific area, power or performance constraints are defined for AXI-SDRAM interface as the first step is to obtain a functional design with the required verification setup to ensure its proper operation once fabricated on silicon. The design of the IP covers different aspects in the ASIC design flow: the initial RTL implementation, synthesis, verification at RTL and gate-level simulations and a final power analysis. Final results show that this IP can successfully be integrated with the preDRAC SoC, replacing the custom interface, and obtaining better performance. However, the AXI-SDRAM interface IP can be further improved both in terms of performance and power. |
dc.language.iso | eng |
dc.publisher | Universitat Politècnica de Catalunya |
dc.rights | S'autoritza la difusió de l'obra mitjançant la llicència Creative Commons o similar 'Reconeixement-NoComercial- SenseObraDerivada' |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria civil |
dc.subject.lcsh | Multiprocessors |
dc.subject.lcsh | Electronic circuits |
dc.subject.other | ASIC |
dc.subject.other | AXI |
dc.subject.other | controller |
dc.subject.other | interface |
dc.subject.other | memory |
dc.subject.other | RISC-V |
dc.subject.other | SDR SDRAM |
dc.title | Design of an AXI-SDRAM interface IP in a RISC-V processor |
dc.type | Master thesis |
dc.subject.lemac | Multiprocessadors |
dc.subject.lemac | Circuits electrònics |
dc.identifier.slug | ETSETB-230.148775 |
dc.rights.access | Open Access |
dc.date.updated | 2020-06-12T05:50:18Z |
dc.audience.educationlevel | Màster |
dc.audience.mediator | Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona |