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dc.contributor.authorTrilla Rodríguez, David
dc.contributor.authorHernández Luz, Carles
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2020-05-14T10:40:00Z
dc.date.available2020-05-14T10:40:00Z
dc.date.issued2019
dc.identifier.citationTrilla, D. [et al.]. An approach for detecting power peaks during testing and breaking systematic pathological behavior. A: Euromicro Conference on Digital System Design. "Euromicro Conference on Digital System Design, DSD 2019: 28-30 August 2019, Kallithea, Chalkidiki, Greece". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 538-545.
dc.identifier.isbn978-1-7281-2861-0
dc.identifier.urihttp://hdl.handle.net/2117/187511
dc.description.abstractThe verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on power peaks, which may cause voltage droops and thus, challenge performance to preserve correct operation upon droops. In this line, the use of complex software and hardware in critical embedded systems jeopardizes the confidence that can be placed on the tests carried out during the campaigns performed at analysis. This is so because it is unknown whether tests have triggered the highest power peaks that can occur during operation and whether any such peak can occur systematically. In this paper we propose the use of randomization, already used for timing analysis of real-time systems, as an enabler to guarantee that (1) tests expose those peaks that can arise during operation and (2) peaks cannot occur systematically inadvertently.
dc.description.sponsorshipThis work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No. 772773), and the HiPEAC Network of Excellence. MINECO partially supported Jaume Abella under Ramon y Cajal postdoctoral fellowship (RYC-2013-14717).
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshEmbedded computer systems
dc.subject.lcshReal-time data processing
dc.subject.lcshComputer software -- Reliability
dc.subject.otherTiming
dc.subject.otherProgram processors
dc.subject.otherProbabilistic logic
dc.subject.otherSystematics
dc.subject.otherPower dissipation
dc.subject.otherHardware
dc.titleAn approach for detecting power peaks during testing and breaking systematic pathological behavior
dc.typeConference report
dc.subject.lemacOrdinadors immersos, Sistemes d'
dc.subject.lemacTemps real (Informàtica)
dc.subject.lemacProgramari -- Fiabilitat
dc.identifier.doi10.1109/DSD.2019.00083
dc.identifier.dl19080147
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8875102
dc.rights.accessOpen Access
local.identifier.drac28129934
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//RYC-2013-14717/ES/RYC-2013-14717/
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/772773/EU/Sustainable Performance for High-Performance Embedded Computing Systems/SuPerCom
local.citation.authorTrilla, D.; Hernández, C.; Abella, J.; Cazorla, F. J.
local.citation.contributorEuromicro Conference on Digital System Design
local.citation.publicationNameEuromicro Conference on Digital System Design, DSD 2019: 28-30 August 2019, Kallithea, Chalkidiki, Greece
local.citation.startingPage538
local.citation.endingPage545


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