An approach for detecting power peaks during testing and breaking systematic pathological behavior
Visualitza/Obre
Cita com:
hdl:2117/187511
Tipus de documentText en actes de congrés
Data publicació2019
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Tots els drets reservats. Aquesta obra està protegida pels drets de propietat intel·lectual i
industrial corresponents. Sense perjudici de les exempcions legals existents, queda prohibida la seva
reproducció, distribució, comunicació pública o transformació sense l'autorització del titular dels drets
ProjecteCOMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
RYC-2013-14717 (MINECO-RYC-2013-14717)
SuPerCom - Sustainable Performance for High-Performance Embedded Computing Systems (EC-H2020-772773)
RYC-2013-14717 (MINECO-RYC-2013-14717)
SuPerCom - Sustainable Performance for High-Performance Embedded Computing Systems (EC-H2020-772773)
Abstract
The verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on power peaks, which may cause voltage droops and thus, challenge performance to preserve correct operation upon droops. In this line, the use of complex software and hardware in critical embedded systems jeopardizes the confidence that can be placed on the tests carried out during the campaigns performed at analysis. This is so because it is unknown whether tests have triggered the highest power peaks that can occur during operation and whether any such peak can occur systematically. In this paper we propose the use of randomization, already used for timing analysis of real-time systems, as an enabler to guarantee that (1) tests expose those peaks that can arise during operation and (2) peaks cannot occur systematically inadvertently.
CitacióTrilla, D. [et al.]. An approach for detecting power peaks during testing and breaking systematic pathological behavior. A: Euromicro Conference on Digital System Design. "Euromicro Conference on Digital System Design, DSD 2019: 28-30 August 2019, Kallithea, Chalkidiki, Greece". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 538-545.
Dipòsit legal19080147
ISBN978-1-7281-2861-0
Versió de l'editorhttps://ieeexplore.ieee.org/document/8875102
Fitxers | Descripció | Mida | Format | Visualitza |
---|---|---|---|---|
Trilla et al.pdf | 490,8Kb | Visualitza/Obre |