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A vulnerability factor for ECC-protected memory
dc.contributor.author | Jaulmes, Luc |
dc.contributor.author | Moretó Planas, Miquel |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Casas, Marc |
dc.contributor.other | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2020-05-05T08:06:27Z |
dc.date.available | 2020-05-05T08:06:27Z |
dc.date.issued | 2019 |
dc.identifier.citation | Jaulmes, L. [et al.]. A vulnerability factor for ECC-protected memory. A: IEEE International Symposium on On-Line Testing and Robust System Design. "2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019): 1–3 July 2019, Greece". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 176-181. |
dc.identifier.isbn | 978-1-7281-2490-2 |
dc.identifier.uri | http://hdl.handle.net/2117/186283 |
dc.description.abstract | Fault injection studies and vulnerability analyses have been used to estimate the reliability of data structures in memory. We survey these metrics and look at their adequacy to describe the data stored in ECC-protected memory. We also introduce FEA, a new metric improving on the memory derating factor by ignoring a class of false errors. We measure all metrics using simulations and compare them to the outcomes of injecting errors in real runs. This in-depth study reveals that FEA provides more accurate results than any state-of-the-art vulnerability metric. Furthermore, FEA gives an upper bound on the failure probability due to an error in memory, making this metric a tool of choice to quantify memory vulnerability. Finally, we show that ignoring these false errors reduces the failure rate on average by 12.75% and up to over 45%. |
dc.description.sponsorship | This work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Economy and Competitiveness (contract TIN2015-65316- P), by the Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017- SGR-1328), by the Spanish Government (Severo Ochoa grant SEV-2015- 0493) and by the European Union’s Horizon 2020 research and innovation programme (grant agreements 671697 and 779877). L. Jaulmes has been partially supported by the Spanish Ministry of Education, Culture and Sports under grant FPU2013/06982. M. Moreto and M. Casas have been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramon y Cajal fellowships RYC-2016-21104 and RYC-2017-23269. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Computer software -- Reliability |
dc.subject.lcsh | Fault-tolerant computing |
dc.subject.lcsh | Error-correcting codes (Information theory) |
dc.subject.other | Benchmark testing |
dc.subject.other | Jacobian matrices |
dc.subject.other | Task analysis |
dc.subject.other | Random access memory |
dc.subject.other | Timing |
dc.title | A vulnerability factor for ECC-protected memory |
dc.type | Conference report |
dc.subject.lemac | Programari -- Fiabilitat |
dc.subject.lemac | Tolerància als errors (Informàtica) |
dc.subject.lemac | Codis correctors d'errors (Teoria de la informació) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/IOLTS.2019.8854397 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8854397 |
dc.rights.access | Open Access |
local.identifier.drac | 27851899 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/AEI/RYC-2016-21104 |
dc.relation.projectid | info:eu-repo/grantAgreement/AGAUR/2017 SGR 1414 |
dc.relation.projectid | info:eu-repo/grantAgreement/AGAUR/2017-SGR-1328 |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/ |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//SEV-2015-0493/ES/BARCELONA SUPERCOMPUTING CENTER - CENTRO. NACIONAL DE SUPERCOMPUTACION/ |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platform based on low-power embedded technology/Mont-Blanc 3 |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/779877/EU/Mont-Blanc 2020, European scalable, modular and power efficient HPC processor/Mont-Blanc 2020 |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO/2PE/RYC-2017-23269 |
local.citation.author | Jaulmes, L.; Moreto, M.; Valero, M.; Casas, M. |
local.citation.contributor | IEEE International Symposium on On-Line Testing and Robust System Design |
local.citation.publicationName | 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019): 1–3 July 2019, Greece |
local.citation.startingPage | 176 |
local.citation.endingPage | 181 |