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Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
dc.contributor.author | Jaksic, Zoran |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2013-03-12T13:17:05Z |
dc.date.created | 2012 |
dc.date.issued | 2012 |
dc.identifier.citation | Jaksic, Z.; Canal, R. Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs. A: IEEE International Conference on Computer Design: VLSI in Computers and Processors. "2012 IEEE 30th International Conference on Computer Design (ICCD)". Montreal: IEEE Computer Society Publications, 2012, p. 309-314. |
dc.identifier.isbn | 978-1-4673-3051-0 |
dc.identifier.uri | http://hdl.handle.net/2117/18207 |
dc.description.abstract | In this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post- fabrication/run-time adaptability. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Hardware |
dc.subject.lcsh | Semiconductor storage devices |
dc.title | Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs |
dc.type | Conference report |
dc.subject.lemac | Ordinadors -- Memòries semiconductores |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/ICCD.2012.6378657 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6378657&isnumber=6378602 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 11416916 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Jaksic, Z.; Canal, R. |
local.citation.contributor | IEEE International Conference on Computer Design: VLSI in Computers and Processors |
local.citation.pubplace | Montreal |
local.citation.publicationName | 2012 IEEE 30th International Conference on Computer Design (ICCD) |
local.citation.startingPage | 309 |
local.citation.endingPage | 314 |