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dc.contributor.authorJaksic, Zoran
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2013-03-12T13:17:05Z
dc.date.created2012
dc.date.issued2012
dc.identifier.citationJaksic, Z.; Canal, R. Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs. A: IEEE International Conference on Computer Design: VLSI in Computers and Processors. "2012 IEEE 30th International Conference on Computer Design (ICCD)". Montreal: IEEE Computer Society Publications, 2012, p. 309-314.
dc.identifier.isbn978-1-4673-3051-0
dc.identifier.urihttp://hdl.handle.net/2117/18207
dc.description.abstractIn this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post- fabrication/run-time adaptability.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherIEEE Computer Society Publications
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshSemiconductor storage devices
dc.titleEnhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
dc.typeConference report
dc.subject.lemacOrdinadors -- Memòries semiconductores
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/ICCD.2012.6378657
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6378657&isnumber=6378602
dc.rights.accessRestricted access - publisher's policy
drac.iddocument11416916
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorJaksic, Z.; Canal, R.
upcommons.citation.contributorIEEE International Conference on Computer Design: VLSI in Computers and Processors
upcommons.citation.pubplaceMontreal
upcommons.citation.publishedtrue
upcommons.citation.publicationName2012 IEEE 30th International Conference on Computer Design (ICCD)
upcommons.citation.startingPage309
upcommons.citation.endingPage314


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