Show simple item record

dc.contributor.authorGanapathy, Shrikanth
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorAlexandrescu, Dan
dc.contributor.authorCostenaro, Enrico
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2013-03-11T14:33:59Z
dc.date.created2012
dc.date.issued2012
dc.identifier.citationGanapathy, S. [et al.]. A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. A: IEEE International Conference on Computer Design: VLSI in Computers and Processors. "2012 IEEE 30th International Conference on Computer Design (ICCD)". Montreal: IEEE Computer Society Publications, 2012, p. 472-477.
dc.identifier.isbn978-1-4673-3050-3
dc.identifier.urihttp://hdl.handle.net/2117/18176
dc.description.abstractIn view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment
dc.format.extent6 p.
dc.language.isoeng
dc.publisherIEEE Computer Society Publications
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics
dc.subject.lcshElectronic circuits
dc.titleA novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
dc.typeConference report
dc.subject.lemacCircuits electrònics
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/ICCD.2012.6378681
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6378681&isnumber=6378602
dc.rights.accessRestricted access - publisher's policy
drac.iddocument11417132
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorGanapathy, S.; Canal, R.; Alexandrescu, D.; Costenaro, E.; Gonzalez, A.; Rubio, J.A.
upcommons.citation.contributorIEEE International Conference on Computer Design: VLSI in Computers and Processors
upcommons.citation.pubplaceMontreal
upcommons.citation.publishedtrue
upcommons.citation.publicationName2012 IEEE 30th International Conference on Computer Design (ICCD)
upcommons.citation.startingPage472
upcommons.citation.endingPage477


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder