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dc.contributor.authorVatajelu, Elena Ioana
dc.contributor.authorGómez Pau, Álvaro
dc.contributor.authorRenovell, Michel
dc.contributor.authorFigueras Pàmies, Joan
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2013-02-22T13:45:26Z
dc.date.available2013-02-22T13:45:26Z
dc.date.created2012
dc.date.issued2012
dc.identifier.citation, E. [et al.]. SRAM stability metric under transient noise. A: Design of Circuits and Integrated Systems Conference. "Proceedings of XXVIIth Conference on Design of Circuits and Integrated Systems". Avignon: 2012.
dc.identifier.isbn978-2-9517461-1-4
dc.identifier.urihttp://hdl.handle.net/2117/17943
dc.description.abstractventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well characterized by means of the Static Noise Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. However, a significant number of disturbance sources present a transient behavior which is ignored by the static analysis but has to be taken in consideration for a complete characterization of the cell’s behavior. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage noise is proposed based on determining the energy of the noise signal which is able to flip the cell’s state. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage noise signal able to flip the cell.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshRobust control.
dc.subject.lcshElectronics
dc.titleSRAM stability metric under transient noise
dc.typeConference report
dc.subject.lemacElectrònica
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.rights.accessOpen Access
local.identifier.drac11423008
dc.description.versionPostprint (published version)
local.citation.author, E.; Álvaro Gómez-Pau; Renovell, M.; Figueras, J.
local.citation.contributorDesign of Circuits and Integrated Systems Conference
local.citation.pubplaceAvignon
local.citation.publicationNameProceedings of XXVIIth Conference on Design of Circuits and Integrated Systems


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