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dc.contributor.authorEscuín Blasco, Carlos
dc.contributor.authorMonreal Arnal, Teresa
dc.contributor.authorLlaberia Griñó, José M.
dc.contributor.authorViñals Yúfera, Victor
dc.contributor.authorIbáñez Marín, Pablo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2020-02-18T08:00:41Z
dc.date.available2020-02-18T08:00:41Z
dc.date.issued2019
dc.identifier.citationEscuín, C. [et al.]. STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption. A: International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems. "ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts". European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2019, p. 231-234.
dc.identifier.isbn978-88-905806-7-3
dc.identifier.urihttp://hdl.handle.net/2117/177887
dc.description.abstractCurrent applications demand larger on-chip memory capacity since off-chip memory accesses be-come a bottleneck. However, if we want to achieve this by scaling down the transistor size of SRAM-based Last-Level Caches (LLCs) it may become prohibitive in terms of cost, area and en-ergy. Therefore, other technologies such as STT-RAM are becoming real alternatives to build the LLC in multicore systems. Although STT-RAM bitcells feature high density and low static power, they suffer from other trade-offs. On the one hand, STT-RAM writes are more expensive than STT-RAM reads and SRAM writes. In order to address this asymmetry, we will propose microarchitectural techniques to minimize the number of write operations on STT-RAM cells. On the other hand, reliability also plays an important role. STT-RAM cells suffer from three types of errors: write, read disturbance, and retention errors. Regarding this, we will suggest tech-niques to manage redundant information allowing error detection and information recovery.
dc.format.extent4 p.
dc.language.isoeng
dc.publisherEuropean Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMemory management (Computer science)
dc.subject.lcshCache memory
dc.subject.otherMemory hierarchy
dc.subject.otherLast-level caches
dc.subject.otherNon-volatile memories
dc.subject.otherSTT-RAM
dc.titleSTT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption
dc.typeConference lecture
dc.subject.lemacGestió de memòria (Informàtica)
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
local.identifier.drac26688403
dc.description.versionPostprint (published version)
local.citation.authorEscuín, C.; Monreal, T.; Llaberia, J.; Viñals, V.; Ibáñez, P.
local.citation.contributorInternational Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems
local.citation.publicationNameACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts
local.citation.startingPage231
local.citation.endingPage234


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