STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption
Document typeConference lecture
PublisherEuropean Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)
Rights accessOpen Access
Current applications demand larger on-chip memory capacity since off-chip memory accesses be-come a bottleneck. However, if we want to achieve this by scaling down the transistor size of SRAM-based Last-Level Caches (LLCs) it may become prohibitive in terms of cost, area and en-ergy. Therefore, other technologies such as STT-RAM are becoming real alternatives to build the LLC in multicore systems. Although STT-RAM bitcells feature high density and low static power, they suffer from other trade-offs. On the one hand, STT-RAM writes are more expensive than STT-RAM reads and SRAM writes. In order to address this asymmetry, we will propose microarchitectural techniques to minimize the number of write operations on STT-RAM cells. On the other hand, reliability also plays an important role. STT-RAM cells suffer from three types of errors: write, read disturbance, and retention errors. Regarding this, we will suggest tech-niques to manage redundant information allowing error detection and information recovery.
CitationEscuín, C. [et al.]. STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption. A: International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems. "ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts". European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2019, p. 231-234.
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder