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Protecting RSA hardware accelerators against differential fault analysis through residue checking
dc.contributor.author | Lasheras Mas, Ana |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Rodríguez Luna, Eva |
dc.contributor.author | Cassano, Luca |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2020-01-16T15:57:52Z |
dc.date.available | 2020-01-16T15:57:52Z |
dc.date.issued | 2019 |
dc.identifier.citation | Lasheras, A. [et al.]. Protecting RSA hardware accelerators against differential fault analysis through residue checking. A: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. "2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 1-6. |
dc.identifier.isbn | 978-1-7281-2260-1 |
dc.identifier.uri | http://hdl.handle.net/2117/175113 |
dc.description | © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
dc.description.abstract | Hardware accelerators for cryptographic algorithms are ubiquitously deployed in nowadays consumer and industrial products. Unfortunately, the HW implementations of such algorithms often suffer from vulnerabilities that expose systems to a number of attacks, among which differential fault analysis (DFA). It is therefore crucial to protect cryptographic circuits against such attacks in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting circuits implementing the RSA algorithm against DFA. The proposed solution borrows residue checking from the traditional fault tolerance and applies it to RSA circuits in order to first detect the occurrence a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the proposed solution detects the 100% of the possible fault attacks while leading to a 2.85% area overhead, a 16.67% power consumption increase and with no operating frequency decrease. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica::Criptografia |
dc.subject.lcsh | Public key cryptography |
dc.subject.lcsh | Fault-tolerant computing |
dc.subject.other | Attack resistance |
dc.subject.other | Cryptographic hardware accelerators |
dc.subject.other | Differential fault analysis |
dc.subject.other | Hardware security |
dc.title | Protecting RSA hardware accelerators against differential fault analysis through residue checking |
dc.type | Conference report |
dc.subject.lemac | Criptografia |
dc.subject.lemac | Tolerància als errors (Informàtica) |
dc.contributor.group | Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems |
dc.identifier.doi | 10.1109/DFT.2019.8875320 |
dc.identifier.dl | 19079069 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8875320 |
dc.rights.access | Open Access |
local.identifier.drac | 26236212 |
dc.description.version | Postprint (author's final draft) |
local.citation.author | Lasheras, A.; Canal, R.; Rodríguez, E.; Cassano, L. |
local.citation.contributor | IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems |
local.citation.publicationName | 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
local.citation.startingPage | 1 |
local.citation.endingPage | 6 |