Protecting RSA hardware accelerators against differential fault analysis through residue checking
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Hardware accelerators for cryptographic algorithms are ubiquitously deployed in nowadays consumer and industrial products. Unfortunately, the HW implementations of such algorithms often suffer from vulnerabilities that expose systems to a number of attacks, among which differential fault analysis (DFA). It is therefore crucial to protect cryptographic circuits against such attacks in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting circuits implementing the RSA algorithm against DFA. The proposed solution borrows residue checking from the traditional fault tolerance and applies it to RSA circuits in order to first detect the occurrence a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the proposed solution detects the 100% of the possible fault attacks while leading to a 2.85% area overhead, a 16.67% power consumption increase and with no operating frequency decrease.
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CitationLasheras, A. [et al.]. Protecting RSA hardware accelerators against differential fault analysis through residue checking. A: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. "2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 1-6.
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