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dc.contributor.authorAgosta, Giovanni
dc.contributor.authorFornaciari, William
dc.contributor.authorAtienza, David
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorCilardo, Alessandro
dc.contributor.authorFlich Cardo, José
dc.contributor.authorHernández Luz, Carles
dc.contributor.authorKulczewski, Michal
dc.contributor.authorMassari, Giuseppe
dc.contributor.authorTornero Gavilá, Rafael
dc.contributor.authorZapater Sancho, Marina
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationAgosta, G. [et al.]. Challenges in deeply heterogeneous high performance systems. A: Euromicro Conference on Digital System Design. "Euromicro Conference on Digital System Design, DSD 2019: 28-30 August 2019, Kallithea, Chalkidiki, Greece". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 428-435.
dc.description© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractRECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted at exploring new High-Performance Computing (HPC) technologies. RECIPE aims at introducing a hierarchical runtime resource management infrastructure to optimize energy efficiency and minimize the occurrence of thermal hotspots, while enforcing the time constraints imposed by the applications and ensuring reliability for both time-critical and throughput-oriented computation that run on deeply heterogeneous accelerator-based systems. This paper presents a detailed overview of RECIPE, identifying the fundamental challenges as well as the key innovations addressed by the project, which span run-time management, heterogeneous computing architectures, HPC memory/interconnection infrastructures, thermal modelling, reliability, programming models, and timing analysis. For each of these areas, the paper describes the relevant state of the art as well as the specific actions that the project will take to effectively address the identified technological challenges.
dc.format.extent8 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshEnergy conservation
dc.subject.lcshEmbedded computer systems
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherComputer architecture
dc.subject.otherParallel processing
dc.subject.otherPower aware computing
dc.subject.otherResource allocation
dc.subject.otherHigh-performance computing technologies
dc.subject.otherHierarchical runtime resource management infrastructure
dc.subject.otherEnergy efficiency
dc.subject.otherThermal hotspots
dc.subject.otherTime constraints
dc.subject.otherThroughput-oriented computation
dc.subject.otherDeeply heterogeneous accelerator-based systems
dc.subject.otherRun-time management
dc.subject.otherHeterogeneous computing architectures
dc.subject.otherThermal modelling
dc.subject.otherDeeply heterogeneous high performance systems
dc.subject.otherHeterogeneous exascale systems
dc.subject.otherH2020 FETHPC programme
dc.subject.otherReliable power and time-constraints-aware predictive management of heterogeneous exascale systems
dc.subject.otherTime-critical computation
dc.subject.otherComputational modeling
dc.subject.otherResource management
dc.subject.otherThermal management
dc.subject.otherHeterogeneous computing
dc.subject.otherRun-time management
dc.titleChallenges in deeply heterogeneous high performance systems
dc.typeConference report
dc.subject.lemacEnergia -- Estalvi
dc.subject.lemacOrdinadors immersos, Sistemes d'
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/801137/EU/REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems/RECIPE
local.citation.authorAgosta, G.; Fornaciari, W.; Atienza, D.; Canal, R.; Cilardo, A.; Flich, J; Hernández, C.; Kulczewski, M.; Massari, G.; Tornero, R.; Zapater, M.
local.citation.contributorEuromicro Conference on Digital System Design
local.citation.publicationNameEuromicro Conference on Digital System Design, DSD 2019: 28-30 August 2019, Kallithea, Chalkidiki, Greece

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