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dc.contributor.authorRodríguez Montañés, Rosa
dc.contributor.authorArumi Delgado, Daniel
dc.contributor.authorFigueras Pàmies, Joan
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2019-10-09T10:30:48Z
dc.date.available2019-10-09T10:30:48Z
dc.date.issued2019-07-17
dc.identifier.citationRodriguez-Montanes, R.; Arumi, D.; Figueras, J. Postbond test of through-silicon vias with resistive open defects. "IEEE transactions on very large scale integration (VLSI) systems", 17 Juliol 2019, vol. 27, núm 11, p.2596-2607
dc.identifier.issn1063-8210
dc.identifier.urihttp://hdl.handle.net/2117/169517
dc.description© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
dc.description.abstractThrough-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the oxide, or misalignment during bonding, among others. Although considerable research effort has been made to improve the coverage of TSV testing, little attention has been paid to weak (resistive) open defects causing small delays. In this work, a postbond oscillation test strategy to detect such small delay defects is proposed. Variations in the duty cycle of transmitted signals after unbalanced logic gates are shown to help in the detection of weak open defects in TSVs. HSPICE simulations, including process parameter variations, have been considered, and results show the effectiveness of the method in the detection of weak open defects above 1 kO . Experimental work on a 65-nm IC also corroborates the detection capability of the proposal
dc.format.extent12 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshThree-dimensional integrated circuits
dc.subject.otherDesign for testability
dc.subject.otherDuty cycle (DC)
dc.subject.otherResistive open defect
dc.subject.otherThree-dimensional integrated circuit (3-D IC)
dc.subject.otherThrough-silicon via (TSV)
dc.subject.otherTSV testing.
dc.titlePostbond test of through-silicon vias with resistive open defects
dc.typeArticle
dc.subject.lemacCircuits integrats tridimensionals
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.identifier.doi10.1109/TVLSI.2019.2925971
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8765618
dc.rights.accessOpen Access
local.identifier.drac25850406
dc.description.versionPostprint (published version)
local.citation.authorRodriguez-Montanes, R.; Arumi, D.; Figueras, J.
local.citation.publicationNameIEEE transactions on very large scale integration (VLSI) systems
local.citation.startingPage2596
local.citation.endingPage2607


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