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dc.contributorZapata Rodríguez, Mireya Patricia
dc.contributorMadrenas Boadas, Jordi
dc.contributor.authorGattuso, Roberto
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2019-10-03T21:06:47Z
dc.date.available2020-10-04T00:27:47Z
dc.date.issued2019-07
dc.identifier.urihttp://hdl.handle.net/2117/169144
dc.description.abstractThis thesis work is focussed on the scalability and virtualization enhancement of HEENS architecture, which is a spiking neural hardware emulator. All blocks are described in VHDL, simulated to check their behaviour and finally the whole system is synthesized and implemented on a PSOC, in order to verify time constraints and area occupied. In particular, all the improvements made concern the processing element array, which represents spiking neurons that have to be emulated. Finally the architecture has a new spike distribution structure, making the system more scalable, and virtualization is introduced, in order to extend the array without requiring more resources, thus saving space on the board.
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshNeural networks (Computer science)
dc.subject.lcshDetectors
dc.subject.otherHEENS
dc.subject.otherSNN
dc.subject.otherSpiking Neural Network
dc.subject.otherVirtualization
dc.titleScalability and Virtualization enhancement in Spiking Neural Hardware based on PSOC
dc.typeMaster thesis
dc.subject.lemacXarxes neuronals (Informàtica)
dc.subject.lemacDetectors
dc.identifier.slugETSETB-230.143799
dc.rights.accessOpen Access
dc.date.updated2019-07-29T05:51:32Z
dc.audience.educationlevelMàster
dc.audience.mediatorEscola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona


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