Scalability and Virtualization enhancement in Spiking Neural Hardware based on PSOC

Abstract

This thesis work is focussed on the scalability and virtualization enhancement of HEENS architecture, which is a spiking neural hardware emulator. All blocks are described in VHDL, simulated to check their behaviour and finally the whole system is synthesized and implemented on a PSOC, in order to verify time constraints and area occupied. In particular, all the improvements made concern the processing element array, which represents spiking neurons that have to be emulated. Finally the architecture has a new spike distribution structure, making the system more scalable, and virtualization is introduced, in order to extend the array without requiring more resources, thus saving space on the board.