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dc.contributorCristal Kestelman, Adrián
dc.contributor.authorGonzález Trejo, Alberto
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2019-09-23T11:42:32Z
dc.date.available2019-09-23T11:42:32Z
dc.date.issued2019-07-04
dc.identifier.urihttp://hdl.handle.net/2117/168621
dc.description.abstractIn this work, we leverage an open source simulation framework to evaluate different memory scheduling algorithms and we provide an architectural design of a memory controller, which is implemented in Verilog and tested on a FPGA platform.
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshEnergy consumption
dc.subject.lcshComputer systems
dc.subject.otherMemory System
dc.subject.otherDDR3
dc.subject.otherSistema de memòria
dc.titleLow Energy DRAM Controller for Computer Systems
dc.typeMaster thesis
dc.subject.lemacEnergia -- Consum
dc.subject.lemacSistemes informàtics
dc.identifier.slug138170
dc.rights.accessOpen Access
dc.date.updated2019-07-11T04:01:30Z
dc.audience.educationlevelMàster
dc.audience.mediatorFacultat d'Informàtica de Barcelona


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