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dc.contributor.authorBosch Pons, Jaume
dc.contributor.authorÁlvarez Martínez, Carlos
dc.contributor.authorJiménez González, Daniel
dc.date.accessioned2019-07-26T13:14:20Z
dc.date.available2019-07-26T13:14:20Z
dc.date.issued2019-05-07
dc.identifier.citationBosch Pons, J.; Álvarez Martínez, C.; Jiménez González, D. Supporting task creation inside FPGA devices. A: BSC Severo Ochoa International Doctoral Symposium (6th: 2019: Barcelona). "Book of abstracts". Barcelona: Barcelona Supercomputing Center, 2019, p. 34-35.
dc.identifier.urihttp://hdl.handle.net/2117/166955
dc.description.abstractThe most common model to use co-processors/accelerators is the master-slave model where the slaves (coprocessors/ accelerators) are driven by a general purpose cpu. This simplifies the management of the accelerators because they cannot actively interact with the runtime and they are just passive slaves that operate over the memory under demand. However, the master-slave model limits system possibilities and introduces synchronization overheads that could be avoided. To overcome those limitations and increase the possibilities of accelerators, we propose extending task based programming models (like OpenMP [1] or OmpSs) to support some runtime APIs inside the FPGA co-processor. As a proof-of-concept, we implemented our proposal over the OmpSs@FPGA environment [2] adding the needed infrastructure in the FPGA bitstream and modifying the existing tools to support creation of children tasks inside a task offloaded to an FPGA accelerator. In addition, we added support to synchronize the children tasks created by a FPGA task regardless they are executed in a SMP host thread or they also target another FPGA accelerator in the same co-processor.
dc.format.extent2 p.
dc.language.isoeng
dc.publisherBarcelona Supercomputing Center
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHigh performance computing
dc.subject.lcshHeterogeneous computing
dc.subject.otherHeterogeneous computing
dc.subject.otherDevice offloading
dc.subject.otherTask based parallel programming models
dc.subject.otherHigh-performance computing
dc.titleSupporting task creation inside FPGA devices
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.subject.lemacComputació heterogènia
dc.rights.accessOpen Access
local.citation.contributorBSC Severo Ochoa International Doctoral Symposium (6th: 2019: Barcelona)
local.citation.pubplaceBarcelona
local.citation.publicationNameBook of abstracts
local.citation.startingPage34
local.citation.endingPage35


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Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain