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dc.contributor.authorBosch, Jaume
dc.contributor.authorTan, Xubin
dc.contributor.authorFilgueras Izquierdo, Antonio
dc.contributor.authorVidal, Miquel
dc.contributor.authorMateu, Marc
dc.contributor.authorJiménez-González, Daniel
dc.contributor.authorÁlvarez, Carlos
dc.contributor.authorMartorell Bofill, Xavier
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorLabarta Mancho, Jesús José
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2019-07-24T09:11:30Z
dc.date.available2019-07-24T09:11:30Z
dc.date.issued2019
dc.identifier.citationBosch, J. [et al.]. Application acceleration on FPGAs with OmpSs@FPGA. A: International Conference on Field-Programmable Technology. "2018 International Conference on Field-Programmable Technology (FPT 2018): Naha, Okinawa, Japan: 10-14 December 2018". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 73-80.
dc.identifier.isbn9781728102153
dc.identifier.urihttp://hdl.handle.net/2117/166688
dc.description© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractOmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous execution, we use OmpSs and OmpSs@FPGA as prototype implementation to develop new ideas for OpenMP. OmpSs@FPGA implements the tasking model with runtime support to automatically exploit all SMP and FPGA resources available in the execution platform. In this paper, we present the OmpSs@FPGA ecosystem, based on the Mercurium compiler and the Nanos++ runtime system. We show how the applications are transformed to run on the SMP cores and the FPGA. The application kernels defined as tasks to be accelerated, using the OmpSs directives are: 1) transformed by the compiler into kernels connected with the proper synchronization and communication ports, 2) extracted to intermediate files, 3) compiled through the FPGA vendor HLS tool, and 4) used to configure the FPGA. Our Nanos++ runtime system schedules the application tasks on the platform, being able to use the SMP cores and the FPGA accelerators at the same time. We present the evaluation of the OmpSs@FPGA environment with the Matrix Multiplication, Cholesky and N-Body benchmarks, showing the internal details of the execution, and the performance obtained on a Zynq Ultrascale+ MPSoC (up to 128x). The source code uses OmpSs@FPGA annotations and different Vivado HLS optimization directives are applied for acceleration.
dc.description.sponsorshipThis work is partially supported by the European Union H2020 program through the EuroEXA project (grant 754337), and HiPEAC (GA 687698), by the Spanish Government through Programa Severo Ochoa (SEV-2015- 0493), by the Spanish Ministry of Science and Technology (TIN2015-65316-P) and the Departament d’Innovació Universitats i Empresa de la Generalitat de Catalunya, under project MPEXPAR: Models de Programació i Entorns d’Execució Paral·lels (2014-SGR-1051).
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshField programmable gate arrays
dc.subject.otherTask analysis
dc.subject.otherField programmable gate arrays
dc.subject.otherRuntime
dc.subject.otherSwitched mode power supplies
dc.subject.otherTools
dc.subject.otherIP networks
dc.subject.otherKernel
dc.titleApplication acceleration on FPGAs with OmpSs@FPGA
dc.typeConference report
dc.subject.lemacMatrius de portes programables per l'usuari
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/FPT.2018.00021
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8742333
dc.rights.accessOpen Access
local.identifier.drac25640184
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/754337/EU/Co-designed Innovation and System for Resilient Exascale Computing in Europe: From Applications to Silicon/EuroEXA
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/PRI2010-2013/2014 SGR 1051
local.citation.authorBosch, J.; Tan, X.; Filgueras, A.; Vidal, M.; Mateu, M.; Jiménez-González, D.; Álvarez, C.; Martorell, X.; Ayguade, E.; Labarta, J.
local.citation.contributorInternational Conference on Field-Programmable Technology
local.citation.publicationName2018 International Conference on Field-Programmable Technology (FPT 2018): Naha, Okinawa, Japan: 10-14 December 2018
local.citation.startingPage73
local.citation.endingPage80


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