Application acceleration on FPGAs with OmpSs@FPGA
Visualitza/Obre
Cita com:
hdl:2117/166688
Tipus de documentText en actes de congrés
Data publicació2019
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Tots els drets reservats. Aquesta obra està protegida pels drets de propietat intel·lectual i
industrial corresponents. Sense perjudici de les exempcions legals existents, queda prohibida la seva
reproducció, distribució, comunicació pública o transformació sense l'autorització del titular dels drets
ProjecteEuroEXA - Co-designed Innovation and System for Resilient Exascale Computing in Europe: From Applications to Silicon (EC-H2020-754337)
HiPEAC - High Performance and Embedded Architecture and Compilation (EC-H2020-687698)
COMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
HiPEAC - High Performance and Embedded Architecture and Compilation (EC-H2020-687698)
COMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
Abstract
OmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous execution, we use OmpSs and OmpSs@FPGA as prototype implementation to develop new ideas for OpenMP. OmpSs@FPGA implements the tasking model with runtime support to automatically exploit all SMP and FPGA resources available in the execution platform. In this paper, we present the OmpSs@FPGA ecosystem, based on the Mercurium compiler and the Nanos++ runtime system. We show how the applications are transformed to run on the SMP cores and the FPGA. The application kernels defined as tasks to be accelerated, using the OmpSs directives are: 1) transformed by the compiler into kernels connected with the proper synchronization and communication ports, 2) extracted to intermediate files, 3) compiled through the FPGA vendor HLS tool, and 4) used to configure the FPGA. Our Nanos++ runtime system schedules the application tasks on the platform, being able to use the SMP cores and the FPGA accelerators at the same time. We present the evaluation of the OmpSs@FPGA environment with the Matrix Multiplication, Cholesky and N-Body benchmarks, showing the internal details of the execution, and the performance obtained on a Zynq Ultrascale+ MPSoC (up to 128x). The source code uses OmpSs@FPGA annotations and different Vivado HLS optimization directives are applied for acceleration.
Descripció
© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
CitacióBosch, J. [et al.]. Application acceleration on FPGAs with OmpSs@FPGA. A: International Conference on Field-Programmable Technology. "2018 International Conference on Field-Programmable Technology (FPT 2018): Naha, Okinawa, Japan: 10-14 December 2018". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 73-80.
ISBN9781728102153
Versió de l'editorhttps://ieeexplore.ieee.org/document/8742333
Fitxers | Descripció | Mida | Format | Visualitza |
---|---|---|---|---|
Application Acc ... FPGAs with OmpSs@FPGA.pdf | 498,7Kb | Visualitza/Obre |