Show simple item record

dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorLang, Tomas
dc.contributor.authorLlaberia Griñó, José M.
dc.contributor.authorPeiron Guàrdia, Montse
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorNavarro Guerrero, Juan José
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2019-07-24T07:51:30Z
dc.date.available2019-07-24T07:51:30Z
dc.date.issued1992-05
dc.identifier.citationValero, M. [et al.]. Increasing the number of strides for conflict-free vector access. "Computer architecture news", Maig 1992, vol. 20, núm. 2, p. 372-381.
dc.identifier.issn0163-5964
dc.identifier.urihttp://hdl.handle.net/2117/166656
dc.description.abstractAddress transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we extend these schemes to achieve this conflict-free access for a larger number of strides. The basic idea is to perform an out-of-order access to vectors of fixed length, equal to that of the vector registers of the processor. Both matched and unmatched memories are considered: we show that the number of strides is even larger for the latter case. The hardware for address calculations and access control is described and shown to be of similar complexity as that required for access in order.
dc.format.extent10 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshVector processing (Computer science)
dc.subject.lcshParallel computers
dc.subject.lcshComputer storage devices
dc.subject.otherVector processors
dc.subject.otherMulti-module memories
dc.subject.otherVectors with constant stride
dc.subject.otherConflict-free access
dc.titleIncreasing the number of strides for conflict-free vector access
dc.typeArticle
dc.subject.lemacOrdinadors paral·lels
dc.subject.lemacOrdinadors -- Memòries
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1145/146628.140400
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?doid=146628.140400
dc.rights.accessOpen Access
local.identifier.drac654102
dc.description.versionPostprint (author's final draft)
local.citation.authorValero, M.; Lang, T.; Llaberia, J.; Peiron, M.; Ayguade, E.; Navarro, J.
local.citation.publicationNameComputer architecture news
local.citation.volume20
local.citation.number2
local.citation.startingPage372
local.citation.endingPage381


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record