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dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorLang, Tomas
dc.contributor.authorLlaberia Griñó, José M.
dc.contributor.authorPeiron Guàrdia, Montse
dc.contributor.authorNavarro Guerrero, Juan José
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2019-07-24T07:36:54Z
dc.date.available2019-07-24T07:36:54Z
dc.date.issued1991-12
dc.identifier.citationValero, M. [et al.]. Conflict-free strides for vectors in matched memories. "Parallel processing letters", Desembre 1991, vol. 1, núm. 2, p. 95-102.
dc.identifier.issn0129-6264
dc.identifier.urihttp://hdl.handle.net/2117/166653
dc.description.abstractAddress transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. The paper extends these schemes to achieve this conflict-free access for several families. The basic idea is to perform an out-of-order access to vectors of fixed length, equal to that of the vector registers of the processor. The hardware required is similar to that for the access in order.
dc.format.extent8 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshParallel programming (Computer science)
dc.subject.lcshComputer storage devices
dc.subject.lcshVector processing (Computer science)
dc.subject.otherConflict-free access
dc.subject.otherOut-of-order access
dc.subject.otherParallel memory architectures
dc.subject.otherStorage schemes
dc.subject.otherVector access
dc.titleConflict-free strides for vectors in matched memories
dc.typeArticle
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.subject.lemacOrdinadors -- Memòries
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1142/S0129626491000045
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://www.worldscientific.com/doi/abs/10.1142/S0129626491000045
dc.rights.accessOpen Access
local.identifier.drac654115
dc.description.versionPostprint (author's final draft)
local.citation.authorValero, M.; Lang, T.; Llaberia, J.; Peiron, M.; Navarro, J.; Ayguade, E.
local.citation.publicationNameParallel processing letters
local.citation.volume1
local.citation.number2
local.citation.startingPage95
local.citation.endingPage102


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