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dc.contributor.authorAmiri Nezhad, Maryam
dc.contributor.authorBellalta Jiménez, Boris
dc.contributor.authorGuerrero Zapata, Manel
dc.contributor.authorCerdà Alabern, Llorenç
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2012-10-04T11:47:56Z
dc.date.available2012-10-04T11:47:56Z
dc.date.created2012
dc.date.issued2012
dc.identifier.citationAmiri Nezhad, M. [et al.]. Should next generation wireless mesh networks consider dynamic channel access?. A: Baltic Congress on Future Internet Communications. "2nd Baltic Congress on Future Internet Communications, 25-27 April 2012, Vilnius, Lithuania". Vilnius: 2012, p. 32-39.
dc.identifier.isbn978-146731671-2
dc.identifier.urihttp://hdl.handle.net/2117/16643
dc.description.abstractIn today’s computer architectures, many scientific applications are considered to be memory bound. The memory wall, i.e. the large disparity between a processor’s speed and the required time to access off-chip memory, is a yet-to-be-solved problem that can greatly reduce performance and make us underutilise the processors capabilities. Many different approaches have been proposed to tackle this problem, such as the addition of a large cache hierarchy, multithreading or speculative data prefetching. Most of these approaches rely on the prediction of the application’s future behaviour, something that should not be necessary as this information is known by the programmer and is located in the application itself. Instead of designing hardware that attempts to guess the future, the goal should be to provide the programmer with the hardware support required to decide when the data is transferred and where is it transferred to. With this goal in mind, we introduce the Data Transfer Engine, a runtime-assisted, software prefetcher that exploits the information provided by the programmer in order to place data in the cache hierarchy close to the processor that will make use of it. The DTE can not only significantly reduce stall time due to cache misses but, more importantly, it allows us to design new computer architectures that are able to tolerate very high memory latencies.
dc.format.extent8 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshData recovery (Computer science)
dc.titleShould next generation wireless mesh networks consider dynamic channel access?
dc.typeConference lecture
dc.subject.lemacDades -- Recuperació (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CNDS - Xarxes de Computadors i Sistemes Distribuïts
dc.identifier.doi10.1109/BCFIC.2012.6217976
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
local.identifier.drac10740500
dc.description.versionPreprint
local.citation.authorAmiri Nezhad, M.; Bellalta, B.; Guerrero, M.; Cerdà, L.
local.citation.contributorBaltic Congress on Future Internet Communications
local.citation.pubplaceVilnius
local.citation.publicationName2nd Baltic Congress on Future Internet Communications, 25-27 April 2012, Vilnius, Lithuania
local.citation.startingPage32
local.citation.endingPage39


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Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain