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dc.contributor.authorPalomo, Xavier
dc.contributor.authorMezzetti, Enrico
dc.contributor.authorAbella, Jaume
dc.contributor.authorBril, Reinder J.
dc.contributor.authorCazorla, Francisco J.
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2019-07-18T10:57:51Z
dc.date.available2019-07-18T10:57:51Z
dc.date.issued2019-06-24
dc.identifier.citationPalomo, X. [et al.]. Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems. A: "2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)". IEEE, 2019, p. 15-28.
dc.identifier.isbn978-1-7281-0678-6
dc.identifier.urihttp://hdl.handle.net/2117/166419
dc.description.abstractCommercially available Off The Shelf (COTS) multicores have been assessed as the baseline computing platform even in the most conservative real-time domains. Multicore contention arising on shared hardware resources, with its circular dependence with scheduling, is among the most challenging issues that require urgent attention before multicores can be fully embraced for real-time computing. In the context of static scheduling, still the most used scheduling approach in real-time industries, we propose an ILP formulation for computing the worst-case contention delay suffered by a task due to interference on a shared bus. Our model provides accurate contention delay bounds that avoid unnecessary over-accounting of conflicts between bus requests, by considering contention effects at system-level (i.e., across tasks) rather than at task-level only. This allows precisely capturing the interdependence between timing interference of conflicting requests, issued in parallel by other cores (tasks), and the identification of the particular set of tasks co-running on those cores. We assess our technique both analytically and empirically on a real COTS multicore platform. We show, via extensive evaluation, that jointly accounting for worst-case task overlapping and request distribution scenarios always provides tighter contention bounds when compared to state-of-the-art solutions.
dc.description.sponsorshipThis work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Unions Horizon 2020 research and innovation programme (grant agreement No. 772773), the European Union’s Regional Development Fund (ERDF) within the framework of the ERDF (FEDER) program in Catalonia 2014-2020 under the grant SDESI (2016 PROD00115), and the HiPEAC Network of Excellence. Jaume Abella and Enrico Mezzetti have been partially supported by MINECO under Ramon y Cajal and Juan de la Cierva-Incorporación postdoctoral fellowships number RYC-2013-14717 and IJCI-2016-27396 respectively.
dc.format.extent14 p.
dc.language.isoeng
dc.publisherIEEE
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshHigh performance computing
dc.subject.otherMulticore contention
dc.subject.otherILP
dc.subject.otherCOTS
dc.subject.otherStatic scheduling
dc.titleAccurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems
dc.typeConference lecture
dc.subject.lemacSupercomputadors
dc.identifier.doi10.1109/RTAS.2019.00010
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8743282
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/PE2013-2016/TIN2015-65316-P
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/PE2013-2016/RYC-2013-14717
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/772773/EU/Sustainable Performance for High-Performance Embedded Computing Systems/SuPerCom
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/PE2013-2016/IJCI- 2016-27396
upcommons.citation.publishedtrue
upcommons.citation.publicationName2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
upcommons.citation.startingPage15
upcommons.citation.endingPage28


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