Static task mapping for tiled chip multiprocessors with multiple voltage islands
Document typeConference report
Rights accessRestricted access - publisher's policy
The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple pre-defined voltage islands for power management. The CMPs are assumed to contain different classes of processing elements with multiple voltage/frequency execution modes to better cover a large range of applications. Task mapping is performed with awareness of both on-chip and off-chip memory traffic, and communication constraints such as the link and memory bandwidth. A novel mapping approach based on Extremal Optimization is proposed for large-scale CMPs. This new combinatorial optimization method has delivered very good results in quality and computational cost when compared to the classical simulated annealing.
CitationNikitin, N.; Cortadella, J. Static task mapping for tiled chip multiprocessors with multiple voltage islands. A: International Conference on Architecture of Computing Systems. "Architecture of Computing Systems – ARCS 2012. 25th International Conference. Munich, Germany, February 28 – March 2, 2012 Proceedings". Springer Verlag, 2012, p. 50-62.