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dc.contributor.authorBerna Juan, Alejandro
dc.contributor.authorJiménez Castells, Marta
dc.contributor.authorLlaberia Griñó, José M.
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2012-07-20T15:21:50Z
dc.date.available2012-07-20T15:21:50Z
dc.date.created2012-01
dc.date.issued2012-01
dc.identifier.citationBerna, A.; Jimenez, M.; Llaberia, J. "Vectorized register tiling". 2012.
dc.identifier.urihttp://hdl.handle.net/2117/16308
dc.description.abstractIn the last years, there has been much effort in commercial compilers (icc, gcc) to exploit efficiently the SIMD capabilities and the memory hierarchy that the current processors offer. However, the small numbers of compilers that can automatically exploit these characteristics achieve in most cases unsatisfactory results. Therefore, the programmers often need to apply by hand the optimizations to the source code, write manually the code in assembly or use compiler built-in functions (such intrinsics) to achieve high performance. In this work, we present source-to-source transformations that help commercial compilers exploiting the memory hierarchy and generating efficient SIMD code. Results obtained on our experiments show that our solutions achieve as excellent performance as hand-optimized vendor-supplied numerical libraries (written in assembly).
dc.format.extent2 p.
dc.language.isoeng
dc.relation.ispartofseriesUPC-DAC-RR-CAP-2012-4
dc.subjectÀrees temàtiques de la UPC::Informàtica::Programació
dc.subject.lcshParallel programming (Computer science)
dc.titleVectorized register tiling
dc.typeExternal research report
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://www.ac.upc.edu/app/research-reports/html/2012/5/abstractAndPoster.pdf
dc.rights.accessOpen Access
drac.iddocument9638077
dc.description.versionPreprint
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
upcommons.citation.authorBerna, A.; Jimenez, M.; Llaberia, J.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameVectorized register tiling


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