Vectorized register tiling
Document typeExternal research report
Rights accessOpen Access
European Commission's projectHIPEAC - High Performance and Embedded Architecture and Compilation (EC-FP7-217068)
In the last years, there has been much effort in commercial compilers (icc, gcc) to exploit efficiently the SIMD capabilities and the memory hierarchy that the current processors offer. However, the small numbers of compilers that can automatically exploit these characteristics achieve in most cases unsatisfactory results. Therefore, the programmers often need to apply by hand the optimizations to the source code, write manually the code in assembly or use compiler built-in functions (such intrinsics) to achieve high performance. In this work, we present source-to-source transformations that help commercial compilers exploiting the memory hierarchy and generating efficient SIMD code. Results obtained on our experiments show that our solutions achieve as excellent performance as hand-optimized vendor-supplied numerical libraries (written in assembly).
CitationBerna, A.; Jimenez, M.; Llaberia, J. "Vectorized register tiling". 2012.
Is part ofUPC-DAC-RR-CAP-2012-4
URL other repositoryhttps://www.ac.upc.edu/app/research-reports/html/2012/5/abstractAndPoster.pdf