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dc.contributor.authorAymerich Capdevila, Nivard
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2012-07-17T17:35:56Z
dc.date.created2012-07
dc.date.issued2012-07
dc.identifier.citationAymerich, N.; Rubio, J.A. Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy. "Microprocessors and microsystems", Juliol 2012, vol. 36, núm. 5, p. 420-426.
dc.identifier.issn0141-9331
dc.identifier.urihttp://hdl.handle.net/2117/16281
dc.description.abstractOne of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a fault-tolerant nanoscale architecture based on the implementation of logic systems with Averaging Cells Linear Threshold Gates (AC-LTGs). We compare the tolerance to manufacturing and environment deviation of our approach and the well known NAND multiplexing technique. We show that the AC-LTG is a valuable alternative in specific nanoscale conditions.
dc.format.extent7 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals
dc.subject.lcshIntegrated circuits --Fault tolerance
dc.titleFault-tolerant nanoscale architecture based on linear threshold gates with redundancy
dc.typeArticle
dc.subject.lemacTolerància als errors (Enginyeria)
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1016/j.micpro.2012.02.003
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://dx.doi.org/10.1016/j.micpro.2012.02.003
dc.rights.accessRestricted access - publisher's policy
drac.iddocument10680492
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS
dc.date.lift10000-01-01
upcommons.citation.authorAymerich, N.; Rubio, J.A.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameMicroprocessors and microsystems
upcommons.citation.volume36
upcommons.citation.number5
upcommons.citation.startingPage420
upcommons.citation.endingPage426


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Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain