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dc.contributor.authorMaric, Bojan
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2012-06-14T11:58:54Z
dc.date.created2012
dc.date.issued2012
dc.identifier.citationMaric, B.; Abella, J.; Valero, M. ADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches. A: ACM Great Lakes Symposium on VLSI. "GLSVLSI - Proceedings of the ACM Great Lakes Symposium on VLSI". 2012, p. 245-250.
dc.identifier.isbn978-145031244-8
dc.identifier.urihttp://hdl.handle.net/2117/16043
dc.description.abstractSemiconductor technology evolution enables the design of ultra-low-cost chips (e.g., below 1 USD) required for new market segments such as environment, urban life and body monitoring, etc. Recently, hybrid-operation (high Vcc, ultra-low Vcc) single-Vcc-domain cache designs have been proposed to tackle the needs of those chips. However, existing data management policies are far from being optimal during high Vcc operation. This paper presents ADAM, a new and extremely simple Adaptive Data Management mechanism, which is tailored to detect hit distribution and changing application conditions dynamically at ne grain with negligible hardware overhead. ADAM is proven to save signi cant energy (29% on average) in L1 caches with negligible performance degradation (1.7% on average), thus improving the energy-delay product (EDP) noticeably across di erent cache con gurations with respect to all existing data management approaches.
dc.format.extent6 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshSemiconductor storage devices
dc.subject.lcshADAM (Adaptative data management mechanism)
dc.titleADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches
dc.typeConference report
dc.subject.lemacMemòria cau
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1145/2206781.2206840
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac10542357
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorMaric, B.; Abella, J.; Valero, M.
local.citation.contributorACM Great Lakes Symposium on VLSI
local.citation.publicationNameGLSVLSI - Proceedings of the ACM Great Lakes Symposium on VLSI
local.citation.startingPage245
local.citation.endingPage250


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