A low cost split-issue technique to improve performance of SMT clustered VLIW processors
Tipo de documentoTexto en actas de congreso
Fecha de publicación2010
Condiciones de accesoAcceso abierto
Abstract—Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreading (SMT) is a popular technique for improving processor performance. To maintain execution semantics, a VLIW instruction needs to be issued in entirety, which restricts the opportunities in SMT. Split-issue at operation-level is a technique that allows issuing a VLIW instruction in parts without breaking execution semantics. Issuing an instruction in parts allows non-conflicting part of an instruction to be issued along with other instructions and improves SMT performance. However, implementing splitissue at operation-level requires complex structures and is not practical for an embedded VLIW processor. This paper proposes cluster-level split-issue, which implements split-issue at a cluster-level boundary for clustered VLIW processors. Cluster-level split-issue has a very low hardware overhead in contrast to split-issue at operation-level. Experimental results show that cluster-level split-issue, despite being more restrictive than split-issue at operation-level, achieves similar performance and improves SMT performance significantly.
CitaciónGupta, M.; Sanchez, F.; Llosa, J. A low cost split-issue technique to improve performance of SMT clustered VLIW processors. A: IEEE International Parallel and Distributed Processing Symposium. "Proceedings of the IEEE International Symposium on Parallel & Distributed Processing 2010". Atlanta: 2010, p. 1-12.