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Transient noise failures in SRAM cells: dynamic noise margin metric
dc.contributor.author | Vatajelu, Elena Ioana |
dc.contributor.author | Gómez Pau, Álvaro |
dc.contributor.author | Renovell, Michel |
dc.contributor.author | Figueras Pàmies, Joan |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2012-05-07T09:57:32Z |
dc.date.available | 2012-05-07T09:57:32Z |
dc.date.created | 2011 |
dc.date.issued | 2011 |
dc.identifier.citation | Vatajelu, E. [et al.]. Transient noise failures in SRAM cells : dynamic noise margin metric. A: Asian Test Symposium. "Proceedings of the twentieth Asian test symposium: ATS 2011". New Delhi: IEEE Computer Society Publications, 2011, p. 413-418. |
dc.identifier.isbn | 978-0-7695-4583-7 |
dc.identifier.uri | http://hdl.handle.net/2117/15781 |
dc.description.abstract | Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Hardware |
dc.subject.lcsh | Random access memory -- Reliability |
dc.title | Transient noise failures in SRAM cells: dynamic noise margin metric |
dc.type | Conference report |
dc.subject.lemac | SRAM chips |
dc.contributor.group | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.identifier.doi | 10.1109/ATS.2011.64 |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 10295237 |
dc.description.version | Postprint (published version) |
local.citation.author | Vatajelu, E.; Gómez, A.; Renovell, M.; Figueras, J. |
local.citation.contributor | Asian Test Symposium |
local.citation.pubplace | New Delhi |
local.citation.publicationName | Proceedings of the twentieth Asian test symposium: ATS 2011 |
local.citation.startingPage | 413 |
local.citation.endingPage | 418 |