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dc.contributor.authorCarretero Casado, Javier Sebastián
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorVera Gómez, Javier
dc.contributor.authorChaparro Valero, Pedro Alonso
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Telemàtica
dc.date.accessioned2012-04-26T09:36:34Z
dc.date.available2012-04-26T09:36:34Z
dc.date.created2011
dc.date.issued2011
dc.identifier.citationCarretero, J. [et al.]. Control-flow recovery validation using microarchitectural invariants. A: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. "2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)". 2011, p. 209-216.
dc.identifier.isbn978-0-7695-4556-1
dc.identifier.urihttp://hdl.handle.net/2117/15763
dc.description.abstractProcessors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new challenges to post-Si validation strategies, processes, techniques, tools, and microprocessor hardware features. In this paper we develop a micro architectural technique to speed up the post-Si validation for one of the most complex and difficult to debug control logic pieces in the processor: the control flow recovery mechanisms used by control flow speculation, interrupts and exceptions. Our experiments show that with a small area overhead of 0.14% all post-Si bugs in this complex hardware can be detected in a timely manner, which avoids state pollution and reduces debug time.
dc.format.extent8 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Sistemes d'informació
dc.subject.lcshError detection and correction
dc.subject.lcshPost-Si validation
dc.subject.lcshRAT recovery
dc.titleControl-flow recovery validation using microarchitectural invariants
dc.typeConference report
dc.subject.lemacErrors de sistemes (Enginyeria)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/DFT.2011.32
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac10217579
dc.description.versionPostprint (published version)
local.citation.authorCarretero, J.; Abella, J.; Vera, J.; Chaparro, P.
local.citation.contributorIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
local.citation.publicationName2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
local.citation.startingPage209
local.citation.endingPage216


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