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Achieving high memory performance from heterogeneous architectures with the SARC programming model
dc.contributor.author | Ferrer, Roger |
dc.contributor.author | Beltran Querol, Vicenç |
dc.contributor.author | González Tallada, Marc |
dc.contributor.author | Martorell Bofill, Xavier |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2012-04-10T10:27:39Z |
dc.date.available | 2012-04-10T10:27:39Z |
dc.date.created | 2009 |
dc.date.issued | 2009 |
dc.identifier.citation | Ferrer, R. [et al.]. Achieving high memory performance from heterogeneous architectures with the SARC programming model. A: Workshop on Memory Performance: dealing with Applications, Systems and Architecture. "Proceedings of the 10th MEDEA workshop on MEmory performance: DEaling with Applications, systems and architecture". Raleigh, North Carolina: ACM, 2009, p. 15-21. |
dc.identifier.isbn | 978-1-60558-830-8 |
dc.identifier.uri | http://hdl.handle.net/2117/15712 |
dc.description.abstract | Current heterogeneous multicore architectures, including the Cell/B.E., GPUs, and future developments, like Larrabee, require enormous programming efforts to efficiently run current parallel applications, achieving high performance. In this paper, we want to present the results we obtain from the coding with the SARC Programming Model, of two benchmarks, matrix multiply and conjugate gradient (NAS CG), with respect memory bandwidth. We show some sample loops annotated and the experience that we got trying to have our system executing them efficienly. Results indicate that the programming model is able to achieve up to 85% of the peak memory bandwidth on the Cell/B.E. processor. |
dc.format.extent | 7 p. |
dc.language.iso | eng |
dc.publisher | ACM |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject.lcsh | Software architecture |
dc.subject.lcsh | Conjugate gradient methods |
dc.subject.other | SARC Programming Model |
dc.title | Achieving high memory performance from heterogeneous architectures with the SARC programming model |
dc.type | Conference lecture |
dc.subject.lemac | Programari -- Disseny |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1145/1621960.1621963 |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 2358077 |
dc.description.version | Postprint (published version) |
local.citation.author | Ferrer, R.; Beltran, V.; González, M.; Martorell, X.; Ayguade, E. |
local.citation.contributor | Workshop on Memory Performance: dealing with Applications, Systems and Architecture |
local.citation.pubplace | Raleigh, North Carolina |
local.citation.publicationName | Proceedings of the 10th MEDEA workshop on MEmory performance: DEaling with Applications, systems and architecture |
local.citation.startingPage | 15 |
local.citation.endingPage | 21 |