Achieving high memory performance from heterogeneous architectures with the SARC programming model
Document typeConference lecture
Rights accessRestricted access - publisher's policy
Current heterogeneous multicore architectures, including the Cell/B.E., GPUs, and future developments, like Larrabee, require enormous programming efforts to efficiently run current parallel applications, achieving high performance. In this paper, we want to present the results we obtain from the coding with the SARC Programming Model, of two benchmarks, matrix multiply and conjugate gradient (NAS CG), with respect memory bandwidth. We show some sample loops annotated and the experience that we got trying to have our system executing them efficienly. Results indicate that the programming model is able to achieve up to 85% of the peak memory bandwidth on the Cell/B.E. processor.
CitationFerrer, R. [et al.]. Achieving high memory performance from heterogeneous architectures with the SARC programming model. A: Workshop on Memory Performance: dealing with Applications, Systems and Architecture. "Proceedings of the 10th MEDEA workshop on MEmory performance: DEaling with Applications, systems and architecture". Raleigh, North Carolina: ACM, 2009, p. 15-21.
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