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dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorFigueras Pàmies, Joan
dc.contributor.authorVatajelu, Elena Ioana
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2012-03-26T18:45:53Z
dc.date.available2012-03-26T18:45:53Z
dc.date.created2012-03-01
dc.date.issued2012-03-01
dc.identifier.citationRubio, J. [et al.]. "Process variability in sub-16nm bulk CMOS technology". 2012.
dc.identifier.urihttp://hdl.handle.net/2117/15667
dc.description.abstractThe document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.
dc.format.extent11 p.
dc.language.isoeng
dc.relation.ispartofseriesEEL-121
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits.
dc.titleProcess variability in sub-16nm bulk CMOS technology
dc.typeExternal research report
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.rights.accessOpen Access
local.identifier.drac9879456
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS
local.citation.authorRubio, J.; Figueras, J.; Vatajelu, E.; Canal, R.
local.citation.publicationNameProcess variability in sub-16nm bulk CMOS technology


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