Process variability in sub-16nm bulk CMOS technology
View/Open
Document typeResearch report
Defense date2012-03-01
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial
property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public
communication or transformation of this work are prohibited without permission of the copyright holder
CitationRubio, J. [et al.]. "Process variability in sub-16nm bulk CMOS technology". 2012.
Is part ofEEL-121
Collections
- ARCO - Microarquitectura i Compiladors - Reports de recerca [11]
- Departament d'Enginyeria Electrònica - Reports de recerca [54]
- Departament d'Arquitectura de Computadors - Reports de recerca [178]
- QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat - Reports de recerca [9]
- QINE - Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades - Reports de recerca [9]
- HIPICS - High Performance Integrated Circuits and Systems - Reports de recerca [15]
| Files | Description | Size | Format | View |
|---|---|---|---|---|
| Variability_Scenarios.pdf | 364,7Kb | View/Open |