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dc.contributor.authorRanjan, Rakesh
dc.contributor.authorLatorre Salinas, Fernando
dc.contributor.authorMarcuello Pascual, Pedro
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2012-03-22T12:55:41Z
dc.date.available2012-03-22T12:55:41Z
dc.date.created2011
dc.date.issued2011
dc.identifier.citationRanjan, R. [et al.]. Fg-STP: fine-grain single thread partitioning on multicores. A: International Symposium on High-Performance Computer Architecture (HPCA). "2011 IEEE 17th International Symposium on High Performance Computer Architecture". San Antonio, TX: IEEE Press. Institute of Electrical and Electronics Engineers, 2011, p. 15-24.
dc.identifier.urihttp://hdl.handle.net/2117/15648
dc.description.abstractPower and complexity issues have led the microprocessor industry to shift to Chip Multiprocessors in order to be able to better utilize the additional transistors ensured by Moore's law. While parallel programs are going to be able to take most of the advantage of these CMPs, single thread applications are not equipped to benefit from them. In this paper we propose Fine-Grain Single-Thread Partitioning (Fg-STP), a hardware-only scheme that takes advantage of CMP designs to speedup single-threaded applications. Our proposal improves single thread performance by reconfiguring two cores with the aim of collaborating on the fetching and execution of the instructions. These cores are basically conventional out-of-order cores in which execution is orchestrated using a dedicated hardware that has minimum and localized impact on the original design of the cores. This approach partitions the code at instruction granularity and differs from previous proposals on the extensive use of dependence speculation, replication and communication. These features are combined with the ability to look for parallelism on large instruction windows without any software intervention (no re-compilation or profiling hints are needed). These characteristics allow Fg-STP to speedup single thread by 18% and 7% on average over similar hardware-only approaches like Core Fusion, on medium sized and small sized 2-core CMP respectively for Spec 2006 benchmarks.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherIEEE Press. Institute of Electrical and Electronics Engineers
dc.subjectÀrees temàtiques de la UPC::Informàtica::Llenguatges de programació
dc.subject.lcshMultiprocessing systems
dc.subject.lcshParallel processing (Electronic computers)
dc.titleFg-STP: fine-grain single thread partitioning on multicores
dc.typeConference report
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/HPCA.2011.5749713
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5749713
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac9463709
dc.description.versionPostprint (published version)
local.citation.authorRanjan, R.; Latorre, F.; Marcuello, P.; González, A.
local.citation.contributorInternational Symposium on High-Performance Computer Architecture (HPCA)
local.citation.pubplaceSan Antonio, TX
local.citation.publicationName2011 IEEE 17th International Symposium on High Performance Computer Architecture
local.citation.startingPage15
local.citation.endingPage24


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