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dc.contributor.authorRico Carro, Alejandro
dc.contributor.authorCabarcas, Felipe
dc.contributor.authorVillavieja Prados, Carlos
dc.contributor.authorPavlovic, Milan
dc.contributor.authorVega, Augusto
dc.contributor.authorEtsion, Yoav
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2012-03-22T12:17:59Z
dc.date.available2012-03-22T12:17:59Z
dc.date.created2012-01-23
dc.date.issued2012-01-23
dc.identifier.citationRico, A. [et al.]. On the simulation of large-scale architectures using multiple application abstraction levels. "ACM transactions on architecture and code optimization", 23 Gener 2012, vol. 8, núm. 4, p. 36:1-36:20.
dc.identifier.issn1544-3566
dc.identifier.urihttp://hdl.handle.net/2117/15645
dc.description.abstractSimulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not suitable for simulating large-scale architectures, nor are theymeant for this. Moreover,microarchitecture design decisions are irrelevant, or even misleading, for early processor design stages and high-level explorations. This allows one to raise the abstraction level of the simulated architecture, and also the application abstraction level, as it does not necessarily have to be represented as an instruction stream. In this paper we introduce a definition of different application abstraction levels, and how these are employed in TaskSim, a multi-core architecture simulator, to provide several architecture modeling abstractions, and simulate large-scale architectures with hundreds of cores. We compare the simulation speed of these abstraction levels to the ones in existing simulation tools, and also evaluate their utility and accuracy. Our simulations show that a very high-level abstraction, which may be even faster than native execution, is useful for scalability studies on parallel applications; and that just simulating explicit memory transfers, we achieve accurate simulations for architectures using non-coherent scratchpad memories, with just a 25xslowdown compared to native execution. Furthermore, we revisit trace memory simulation techniques, that are more abstract than instruction-by-instruction simulations and provide an 18x simulation speedup.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshSimulation methods -- Models and modeling
dc.titleOn the simulation of large-scale architectures using multiple application abstraction levels
dc.typeArticle
dc.subject.lemacSimulació, Mètodes de -- Models matemàtics
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac9457174
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248647/EU/ENabling technologies for a programmable many-CORE/ENCORE
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
local.citation.authorRico, A.; Cabarcas, F.; Villavieja, C.; Pavlovic, M.; Vega, A.; Etsion, Y.; Alex Ramirez; Valero, M.
local.citation.publicationNameACM transactions on architecture and code optimization
local.citation.volume8
local.citation.number4
local.citation.startingPage36:1
local.citation.endingPage36:20


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