An abstraction methodology for the evaluation of multi-core multi-threaded architectures
Visualitza/Obre
06005400.pdf (248,0Kb) (Accés restringit)
Sol·licita una còpia a l'autor
Què és aquest botó?
Aquest botó permet demanar una còpia d'un document restringit a l'autor. Es mostra quan:
- Disposem del correu electrònic de l'autor
- El document té una mida inferior a 20 Mb
- Es tracta d'un document d'accés restringit per decisió de l'autor o d'un document d'accés restringit per política de l'editorial
Cita com:
hdl:2117/15378
Tipus de documentText en actes de congrés
Data publicació2011
EditorIEEE Computer Society Publications
Condicions d'accésAccés restringit per política de l'editorial
Llevat que s'hi indiqui el contrari, els
continguts d'aquesta obra estan subjectes a la llicència de Creative Commons
:
Reconeixement-NoComercial-SenseObraDerivada 3.0 Espanya
Abstract
As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to execute the large amount of experiments required to obtain indicative results. To achieve a thorough analysis of the system, software benchmarks or traces are required. In many cases when an analysis is needed most, during the earlier stages of the processor design, benchmarks or traces are not available. Analytical models overcome these limitations but do not provide the fine grain details needed for a deep analysis of these architectures. In this work we present a new methodology to abstract processor architectures, at a level between cycle-accurate and analytical simulators. To apply our methodology we use queueing modeling techniques. Thus, we introduce Q-MAS, a queueing based tool targeting a real chip (the Ultra SPARC T2 processor) and aimed at facilitating the quantification of trade-offs during the design phase of multi-core multi-threaded processor architectures. The results demonstrate that Q-MAS, the tool that we developed, provides accurate results very close to the actual hardware, with a minimal cost of running what-if scenarios.
CitacióZilan, Ruken [et al.]. An abstraction methodology for the evaluation of multi-core multi-threaded architectures. A: IEEE/ACM International Symposium on Modelling, Analysis and Simulation of Computer and Telecommunication Systems. "Proceedings of 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)". IEEE Computer Society Publications, 2011, p. 478-481.
ISBN978-1-4577-0468-0
Versió de l'editorhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6005400
Fitxers | Descripció | Mida | Format | Visualitza |
---|---|---|---|---|
06005400.pdf | 248,0Kb | Accés restringit |