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dc.contributor.authorBerbel Artal, Néstor
dc.contributor.authorFernández García, Raúl
dc.contributor.authorGil Galí, Ignacio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2012-02-01T12:34:46Z
dc.date.available2012-02-01T12:34:46Z
dc.date.created2011
dc.date.issued2011
dc.identifier.citationBerbel, N.; Fernandez, R.; Gil, I. Characterization and modeling of the electromagnetic emission of an ADC converter. A: Progress in Electromagnetics Research Symposium. "Progress In Electromagnetics Research Symposium Proceedings". Marrakesh: 2011.
dc.identifier.isbn978-1-934142-16-5
dc.identifier.urihttp://hdl.handle.net/2117/14909
dc.description.abstractAnalog-to-digital converters (ADC) are widely used in consumer electronics, as well as aeronautic, space and automotive development fields. The ADC clock frequency has been increasing in the latest years due to the continuous downscaling in CMOS technology. This constant rising of the operating frequency implies a significant enhancement of the electromagnetic inference (EMI). Therefore, in order to predict the impact of the EMI on the electronic systems performance, electrical circuit models, involving these EMC issues, are required. In this sense, an electromagnetic model of integrated circuits has been internationally standardized (ICEM model) [1]. This model includes a passive distribution network (PDN), which presents the characteristics of propagations paths of electromagnetic noise and the internal activity (IA), which corresponds to the electromagnetic noise source that originates in switching of active devices in the integrated circuit (IC), measured according to [2]. This work addresses the characterization and modeling of a 10-bit Analog-to-Digital Converter in a 8-small outline integrate circuit (SOIC) package, according to the international standard IEC 62433-2. The ADC has a 3.3 V supply voltage, and an operating frequency of 2.8 MHz. The clock (CLK) corresponds to a square signal with a duty cycle of 50 % and the chip select (CS) is a square waveform of 100 kHz with a duty cycle of 10 %. The input voltage has been chosen to have the worst condition, (i.e. when the ADC output has the maximum number of transitions from 0 to VCC and vice versa). Fig. 1 shows the spectrum of the ADC’s IA measured according to EN 61967-4. The spectrum contains several harmonics due to the CLK and CS signals. The first harmonic is located at 1.4 MHz which corresponds to the frequency of the ADC serial output, and then successive harmonics at even and pair frequencies are produced. All the ADC serial output harmonics present sidebands due to the CS signal. Fig. 2 depicts the return losses parameter (S11) in the power supply pin, which has been obtained by means of a vector network analyzer. The information obtained with S11 is related with the input impedance of the integrated circuit and the characteristics of propagation paths. From these dates, the ICEM model of the ADC converter has been obtained.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència::Convertidors de corrent elèctric
dc.subject.lcshElectric current converters
dc.titleCharacterization and modeling of the electromagnetic emission of an ADC converter
dc.typeConference lecture
dc.subject.lemacConvertidors de corrent elèctric
dc.contributor.groupUniversitat Politècnica de Catalunya. TIEG - Terrassa Industrial Electronics Group
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
drac.iddocument5455795
dc.description.versionPostprint (published version)
upcommons.citation.authorBerbel, N.; Fernandez, R.; Gil, I.
upcommons.citation.contributorProgress in Electromagnetics Research Symposium
upcommons.citation.pubplaceMarrakesh
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProgress In Electromagnetics Research Symposium Proceedings


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