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dc.contributor.authorAndrade Miceli, Dennis Michael
dc.contributor.authorMartorell Cid, Ferran
dc.contributor.authorPons Solé, Marc
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.authorRubio, Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2008-01-15T12:17:54Z
dc.date.available2008-01-15T12:17:54Z
dc.date.created2007-06
dc.date.issued2007-08
dc.identifier.citationAndrade, D.; Martorell, F.; Pons, M.; Moll, F.; Rubio, A.; Power supply noise and logic error probability. European Conference on Circuit Theory and Design 2007.
dc.identifier.isbn1-4244-1342-7
dc.identifier.urihttp://hdl.handle.net/2117/1482
dc.description.abstractVoltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays and a noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in this paper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanisms and shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.
dc.format.extent4
dc.language.isoeng
dc.relation.ispartofEuropean Conference on Circuit Theory and Design
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
dc.subject.lcshIntegrated circuits Computer-aided design Statistical methods.
dc.subject.lcshIntegrated circuits Ultra large scale integration
dc.subject.otherPower supply noise
dc.subject.otherError probability
dc.titlePower supply noise and logic error probability
dc.typeConference report
dc.subject.lemacCircuits integrats a molt gran escala -- Defectes -- Models matemàtics
dc.subject.lemacCircuits integrats -- CMOS
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.date.end2007-08-30
dc.date.start2007-08-27
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access


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